drivers/clk/ingenic/jz4780-cgu.c

Source file repositories/reference/linux-study-clean/drivers/clk/ingenic/jz4780-cgu.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/ingenic/jz4780-cgu.c
Extension
.c
Size
20272 bytes
Lines
809
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Ingenic JZ4780 SoC CGU driver
 *
 * Copyright (c) 2013-2015 Imagination Technologies
 * Author: Paul Burton <paul.burton@mips.com>
 * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
 */

#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/of.h>

#include <dt-bindings/clock/ingenic,jz4780-cgu.h>

#include "cgu.h"
#include "pm.h"

/* CGU register offsets */
#define CGU_REG_CLOCKCONTROL	0x00
#define CGU_REG_LCR				0x04
#define CGU_REG_APLL			0x10
#define CGU_REG_MPLL			0x14
#define CGU_REG_EPLL			0x18
#define CGU_REG_VPLL			0x1c
#define CGU_REG_CLKGR0			0x20
#define CGU_REG_OPCR			0x24
#define CGU_REG_CLKGR1			0x28
#define CGU_REG_DDRCDR			0x2c
#define CGU_REG_VPUCDR			0x30
#define CGU_REG_USBPCR			0x3c
#define CGU_REG_USBRDT			0x40
#define CGU_REG_USBVBFIL		0x44
#define CGU_REG_USBPCR1			0x48
#define CGU_REG_LP0CDR			0x54
#define CGU_REG_I2SCDR			0x60
#define CGU_REG_LP1CDR			0x64
#define CGU_REG_MSC0CDR			0x68
#define CGU_REG_UHCCDR			0x6c
#define CGU_REG_SSICDR			0x74
#define CGU_REG_CIMCDR			0x7c
#define CGU_REG_PCMCDR			0x84
#define CGU_REG_GPUCDR			0x88
#define CGU_REG_HDMICDR			0x8c
#define CGU_REG_MSC1CDR			0xa4
#define CGU_REG_MSC2CDR			0xa8
#define CGU_REG_BCHCDR			0xac
#define CGU_REG_CLOCKSTATUS		0xd4

/* bits within the OPCR register */
#define OPCR_SPENDN0			BIT(7)
#define OPCR_SPENDN1			BIT(6)

/* bits within the USBPCR register */
#define USBPCR_USB_MODE			BIT(31)
#define USBPCR_IDPULLUP_MASK	(0x3 << 28)
#define USBPCR_COMMONONN		BIT(25)
#define USBPCR_VBUSVLDEXT		BIT(24)
#define USBPCR_VBUSVLDEXTSEL	BIT(23)
#define USBPCR_POR				BIT(22)
#define USBPCR_SIDDQ			BIT(21)
#define USBPCR_OTG_DISABLE		BIT(20)
#define USBPCR_COMPDISTUNE_MASK	(0x7 << 17)
#define USBPCR_OTGTUNE_MASK		(0x7 << 14)
#define USBPCR_SQRXTUNE_MASK	(0x7 << 11)
#define USBPCR_TXFSLSTUNE_MASK	(0xf << 7)
#define USBPCR_TXPREEMPHTUNE	BIT(6)
#define USBPCR_TXHSXVTUNE_MASK	(0x3 << 4)
#define USBPCR_TXVREFTUNE_MASK	0xf

/* bits within the USBPCR1 register */
#define USBPCR1_REFCLKSEL_SHIFT	26
#define USBPCR1_REFCLKSEL_MASK	(0x3 << USBPCR1_REFCLKSEL_SHIFT)
#define USBPCR1_REFCLKSEL_CORE	(0x2 << USBPCR1_REFCLKSEL_SHIFT)
#define USBPCR1_REFCLKDIV_SHIFT	24
#define USBPCR1_REFCLKDIV_MASK	(0x3 << USBPCR1_REFCLKDIV_SHIFT)
#define USBPCR1_REFCLKDIV_19_2	(0x3 << USBPCR1_REFCLKDIV_SHIFT)
#define USBPCR1_REFCLKDIV_48	(0x2 << USBPCR1_REFCLKDIV_SHIFT)
#define USBPCR1_REFCLKDIV_24	(0x1 << USBPCR1_REFCLKDIV_SHIFT)
#define USBPCR1_REFCLKDIV_12	(0x0 << USBPCR1_REFCLKDIV_SHIFT)
#define USBPCR1_USB_SEL			BIT(28)
#define USBPCR1_WORD_IF0		BIT(19)
#define USBPCR1_WORD_IF1		BIT(18)

/* bits within the USBRDT register */
#define USBRDT_VBFIL_LD_EN		BIT(25)
#define USBRDT_USBRDT_MASK		0x7fffff

Annotation

Implementation Notes