drivers/clk/mediatek/clk-mt2712-apmixedsys.c

Source file repositories/reference/linux-study-clean/drivers/clk/mediatek/clk-mt2712-apmixedsys.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/mediatek/clk-mt2712-apmixedsys.c
Extension
.c
Size
5706 bytes
Lines
169
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2017 MediaTek Inc.
 *                    Weiyi Lu <weiyi.lu@mediatek.com>
 * Copyright (c) 2023 Collabora Ltd.
 *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
 */
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/platform_device.h>

#include "clk-pll.h"
#include "clk-mtk.h"

#include <dt-bindings/clock/mt2712-clk.h>

#define MT2712_PLL_FMAX		(3000UL * MHZ)

#define CON0_MT2712_RST_BAR	BIT(24)

#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
			_pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,	\
			_tuner_en_bit, _pcw_reg, _pcw_shift,		\
			_div_table) {					\
		.id = _id,						\
		.name = _name,						\
		.reg = _reg,						\
		.pwr_reg = _pwr_reg,					\
		.en_mask = _en_mask,					\
		.flags = _flags,					\
		.rst_bar_mask = CON0_MT2712_RST_BAR,			\
		.fmax = MT2712_PLL_FMAX,				\
		.pcwbits = _pcwbits,					\
		.pd_reg = _pd_reg,					\
		.pd_shift = _pd_shift,					\
		.tuner_reg = _tuner_reg,				\
		.tuner_en_reg = _tuner_en_reg,				\
		.tuner_en_bit = _tuner_en_bit,				\
		.pcw_reg = _pcw_reg,					\
		.pcw_shift = _pcw_shift,				\
		.div_table = _div_table,				\
	}

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
			_pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,	\
			_tuner_en_bit, _pcw_reg, _pcw_shift)		\
		PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags,	\
			_pcwbits, _pd_reg, _pd_shift, _tuner_reg,	\
			_tuner_en_reg, _tuner_en_bit, _pcw_reg,		\
			_pcw_shift, NULL)

static const struct mtk_pll_div_table armca35pll_div_table[] = {
	{ .div = 0, .freq = MT2712_PLL_FMAX },
	{ .div = 1, .freq = 1202500000 },
	{ .div = 2, .freq = 500500000 },
	{ .div = 3, .freq = 315250000 },
	{ .div = 4, .freq = 157625000 },
	{ /* sentinel */ }
};

static const struct mtk_pll_div_table armca72pll_div_table[] = {
	{ .div = 0, .freq = MT2712_PLL_FMAX },
	{ .div = 1, .freq = 994500000 },
	{ .div = 2, .freq = 520000000 },
	{ .div = 3, .freq = 315250000 },
	{ .div = 4, .freq = 157625000 },
	{ /* sentinel */ }
};

static const struct mtk_pll_div_table mmpll_div_table[] = {
	{ .div = 0, .freq = MT2712_PLL_FMAX },
	{ .div = 1, .freq = 1001000000 },
	{ .div = 2, .freq = 601250000 },
	{ .div = 3, .freq = 250250000 },
	{ .div = 4, .freq = 125125000 },
	{ /* sentinel */ }
};

static const struct mtk_pll_data plls[] = {
	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100,
	    HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100,
	    HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
	PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000100,
	    0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
	PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100,
	    0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),
	PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000100,
	    0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),
	PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000100,

Annotation

Implementation Notes