drivers/clk/mediatek/clk-mt7988-infracfg.c

Source file repositories/reference/linux-study-clean/drivers/clk/mediatek/clk-mt7988-infracfg.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/mediatek/clk-mt7988-infracfg.c
Extension
.c
Size
14911 bytes
Lines
301
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2023 MediaTek Inc.
 * Author: Sam Shih <sam.shih@mediatek.com>
 * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
 */

#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include "clk-mux.h"
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
#include <dt-bindings/reset/mediatek,mt7988-resets.h>

#define	MT7988_INFRA_RST0_SET_OFFSET	0x70
#define	MT7988_INFRA_RST1_SET_OFFSET	0x80

static DEFINE_SPINLOCK(mt7988_clk_lock);

static const char *const infra_mux_uart0_parents[] __initconst = { "csw_infra_f26m_sel",
								   "uart_sel" };

static const char *const infra_mux_uart1_parents[] __initconst = { "csw_infra_f26m_sel",
								   "uart_sel" };

static const char *const infra_mux_uart2_parents[] __initconst = { "csw_infra_f26m_sel",
								   "uart_sel" };

static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel", "spi_sel" };

static const char *const infra_mux_spi1_parents[] __initconst = { "i2c_sel", "spim_mst_sel" };

static const char *const infra_pwm_bck_parents[] __initconst = { "top_rtc_32p7k",
								 "csw_infra_f26m_sel", "sysaxi_sel",
								 "pwm_sel" };

static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = {
	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_sel"
};

static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = {
	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p1_sel"
};

static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = {
	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p2_sel"
};

static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = {
	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p3_sel"
};

static const struct mtk_mux infra_muxes[] = {
	/* MODULE_CLK_SEL_0 */
	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
			     infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1, -1),
	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
			     infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1, -1),
	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
			     infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1, -1),
	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", infra_mux_spi0_parents,
			     0x0018, 0x0010, 0x0014, 4, 1, -1, -1, -1),
	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", infra_mux_spi1_parents,
			     0x0018, 0x0010, 0x0014, 5, 1, -1, -1, -1),
	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", infra_mux_spi0_parents,
			     0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1),
	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x0018,
			     0x0010, 0x0014, 14, 2, -1, -1, -1),
	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", infra_pwm_bck_parents,
			     0x0018, 0x0010, 0x0014, 16, 2, -1, -1, -1),
	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", infra_pwm_bck_parents,
			     0x0018, 0x0010, 0x0014, 18, 2, -1, -1, -1),
	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", infra_pwm_bck_parents,
			     0x0018, 0x0010, 0x0014, 20, 2, -1, -1, -1),
	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", infra_pwm_bck_parents,
			     0x0018, 0x0010, 0x0014, 22, 2, -1, -1, -1),
	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", infra_pwm_bck_parents,
			     0x0018, 0x0010, 0x0014, 24, 2, -1, -1, -1),
	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", infra_pwm_bck_parents,
			     0x0018, 0x0010, 0x0014, 26, 2, -1, -1, -1),
	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", infra_pwm_bck_parents,
			     0x0018, 0x0010, 0x0014, 28, 2, -1, -1, -1),
	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", infra_pwm_bck_parents,
			     0x0018, 0x0010, 0x0014, 30, 2, -1, -1, -1),
	/* MODULE_CLK_SEL_1 */
	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_o_p0_sel",

Annotation

Implementation Notes