drivers/clk/mediatek/clk-mt8186-mcu.c
Source file repositories/reference/linux-study-clean/drivers/clk/mediatek/clk-mt8186-mcu.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/clk/mediatek/clk-mt8186-mcu.c- Extension
.c- Size
- 1813 bytes
- Lines
- 69
- Domain
- Driver Families
- Bucket
- drivers/clk
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/clk-provider.hlinux/platform_device.hdt-bindings/clock/mt8186-clk.hclk-mtk.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt8186-clk.h>
#include "clk-mtk.h"
static const char * const mcu_armpll_ll_parents[] = {
"clk26m",
"armpll_ll",
"mainpll",
"univpll_d2"
};
static const char * const mcu_armpll_bl_parents[] = {
"clk26m",
"armpll_bl",
"mainpll",
"univpll_d2"
};
static const char * const mcu_armpll_bus_parents[] = {
"clk26m",
"ccipll",
"mainpll",
"univpll_d2"
};
/*
* We only configure the CPU muxes when adjust CPU frequency in MediaTek CPUFreq Driver.
* Other fields like divider always keep the same value. (set once in bootloader)
*/
static struct mtk_composite mcu_muxes[] = {
/* CPU_PLLDIV_CFG0 */
MUX(CLK_MCU_ARMPLL_LL_SEL, "mcu_armpll_ll_sel", mcu_armpll_ll_parents, 0x2A0, 9, 2),
/* CPU_PLLDIV_CFG1 */
MUX(CLK_MCU_ARMPLL_BL_SEL, "mcu_armpll_bl_sel", mcu_armpll_bl_parents, 0x2A4, 9, 2),
/* BUS_PLLDIV_CFG */
MUX(CLK_MCU_ARMPLL_BUS_SEL, "mcu_armpll_bus_sel", mcu_armpll_bus_parents, 0x2E0, 9, 2),
};
static const struct mtk_clk_desc mcu_desc = {
.composite_clks = mcu_muxes,
.num_composite_clks = ARRAY_SIZE(mcu_muxes),
};
static const struct of_device_id of_match_clk_mt8186_mcu[] = {
{ .compatible = "mediatek,mt8186-mcusys", .data = &mcu_desc },
{ /* sentinel */}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_mcu);
static struct platform_driver clk_mt8186_mcu_drv = {
.driver = {
.name = "clk-mt8186-mcu",
.of_match_table = of_match_clk_mt8186_mcu,
},
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt8186_mcu_drv);
MODULE_DESCRIPTION("MediaTek MT8186 mcusys clocks driver");
MODULE_LICENSE("GPL");
Annotation
- Immediate include surface: `linux/clk-provider.h`, `linux/platform_device.h`, `dt-bindings/clock/mt8186-clk.h`, `clk-mtk.h`.
- Atlas domain: Driver Families / drivers/clk.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.