drivers/clk/mediatek/clk-mt8196-apmixedsys.c

Source file repositories/reference/linux-study-clean/drivers/clk/mediatek/clk-mt8196-apmixedsys.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/mediatek/clk-mt8196-apmixedsys.c
Extension
.c
Size
6519 bytes
Lines
206
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct mtk_pll_desc {
	const struct mtk_pll_data *clks;
	size_t num_clks;
};

static const struct mtk_pll_data apmixed_plls[] = {
	PLL_FENC(CLK_APMIXED_MAINPLL, "mainpll", MAINPLL_CON0, FENC_STATUS_CON0,
		 7, PLL_AO, MAINPLL_CON1, 24, MAINPLL_CON1, 0, 22, 0),
	PLL_FENC(CLK_APMIXED_UNIVPLL, "univpll", UNIVPLL_CON0, FENC_STATUS_CON0,
		 6, 0, UNIVPLL_CON1, 24, UNIVPLL_CON1, 0, 22, 1),
	PLL_FENC(CLK_APMIXED_MSDCPLL, "msdcpll", MSDCPLL_CON0, FENC_STATUS_CON0,
		 5, 0, MSDCPLL_CON1, 24, MSDCPLL_CON1, 0, 22, 2),
	PLL_FENC(CLK_APMIXED_ADSPPLL, "adsppll", ADSPPLL_CON0, FENC_STATUS_CON0,
		 4, 0, ADSPPLL_CON1, 24, ADSPPLL_CON1, 0, 22, 3),
	PLL_FENC(CLK_APMIXED_EMIPLL, "emipll", EMIPLL_CON0, FENC_STATUS_CON0, 3,
		 PLL_AO, EMIPLL_CON1, 24, EMIPLL_CON1, 0, 22, 4),
	PLL_FENC(CLK_APMIXED_EMIPLL2, "emipll2", EMIPLL2_CON0, FENC_STATUS_CON0,
		 2, PLL_AO, EMIPLL2_CON1, 24, EMIPLL2_CON1, 0, 22, 5),
	PLL_FENC(CLK_APMIXED_NET1PLL, "net1pll", NET1PLL_CON0, FENC_STATUS_CON0,
		 1, 0, NET1PLL_CON1, 24, NET1PLL_CON1, 0, 22, 6),
	PLL_FENC(CLK_APMIXED_SGMIIPLL, "sgmiipll", SGMIIPLL_CON0, FENC_STATUS_CON0,
		 0, 0, SGMIIPLL_CON1, 24, SGMIIPLL_CON1, 0, 22, 7),
};

static const struct mtk_pll_desc apmixed_desc = {
	.clks = apmixed_plls,
	.num_clks = ARRAY_SIZE(apmixed_plls),
};

static const struct mtk_pll_data apmixed2_plls[] = {
	PLL_FENC(CLK_APMIXED2_MAINPLL2, "mainpll2", MAINPLL2_CON0, FENC_STATUS_CON0,
		 6, 0, MAINPLL2_CON1, 24, MAINPLL2_CON1, 0, 22, 0),
	PLL_FENC(CLK_APMIXED2_UNIVPLL2, "univpll2", UNIVPLL2_CON0, FENC_STATUS_CON0,
		 5, 0, UNIVPLL2_CON1, 24, UNIVPLL2_CON1, 0, 22, 1),
	PLL_FENC(CLK_APMIXED2_MMPLL2, "mmpll2", MMPLL2_CON0, FENC_STATUS_CON0,
		 4, 0, MMPLL2_CON1, 24, MMPLL2_CON1, 0, 22, 2),
	PLL_FENC(CLK_APMIXED2_IMGPLL, "imgpll", IMGPLL_CON0, FENC_STATUS_CON0,
		 3, 0, IMGPLL_CON1, 24, IMGPLL_CON1, 0, 22, 3),
	PLL_FENC(CLK_APMIXED2_TVDPLL1, "tvdpll1", TVDPLL1_CON0, FENC_STATUS_CON0,
		 2, 0, TVDPLL1_CON1, 24, TVDPLL1_CON1, 0, 22, 4),
	PLL_FENC(CLK_APMIXED2_TVDPLL2, "tvdpll2", TVDPLL2_CON0, FENC_STATUS_CON0,
		 1, 0, TVDPLL2_CON1, 24, TVDPLL2_CON1, 0, 22, 5),
	PLL_FENC(CLK_APMIXED2_TVDPLL3, "tvdpll3", TVDPLL3_CON0, FENC_STATUS_CON0,
		 0, 0, TVDPLL3_CON1, 24, TVDPLL3_CON1, 0, 22, 6),
};

static const struct mtk_pll_desc apmixed2_desc = {
	.clks = apmixed2_plls,
	.num_clks = ARRAY_SIZE(apmixed2_plls),
};

static int clk_mt8196_apmixed_probe(struct platform_device *pdev)
{
	struct clk_hw_onecell_data *clk_data;
	struct device_node *node = pdev->dev.of_node;
	const struct mtk_pll_desc *mcd;
	int r;

	mcd = device_get_match_data(&pdev->dev);
	if (!mcd)
		return -EINVAL;

	clk_data = mtk_alloc_clk_data(mcd->num_clks);
	if (!clk_data)
		return -ENOMEM;

	r = mtk_clk_register_plls(&pdev->dev, mcd->clks, mcd->num_clks,
				  clk_data);
	if (r)
		goto free_apmixed_data;

	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
	if (r)
		goto unregister_plls;

	platform_set_drvdata(pdev, clk_data);

	return r;

unregister_plls:
	mtk_clk_unregister_plls(mcd->clks, mcd->num_clks, clk_data);
free_apmixed_data:
	mtk_free_clk_data(clk_data);
	return r;
}

static void clk_mt8196_apmixed_remove(struct platform_device *pdev)
{
	const struct mtk_pll_desc *mcd = device_get_match_data(&pdev->dev);
	struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);

Annotation

Implementation Notes