drivers/clk/mediatek/clk-mt8196-topckgen.c

Source file repositories/reference/linux-study-clean/drivers/clk/mediatek/clk-mt8196-topckgen.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/mediatek/clk-mt8196-topckgen.c
Extension
.c
Size
30582 bytes
Lines
986
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2025 MediaTek Inc.
 *                    Guangjie Song <guangjie.song@mediatek.com>
 * Copyright (c) 2025 Collabora Ltd.
 *                    Laura Nao <laura.nao@collabora.com>
 */
#include <dt-bindings/clock/mediatek,mt8196-clock.h>

#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>

#include "clk-mtk.h"
#include "clk-mux.h"

/* MUX SEL REG */
#define CLK_CFG_UPDATE		0x0004
#define CLK_CFG_UPDATE1		0x0008
#define CLK_CFG_UPDATE2		0x000c
#define CLK_CFG_0		0x0010
#define CLK_CFG_0_SET		0x0014
#define CLK_CFG_0_CLR		0x0018
#define CLK_CFG_1		0x0020
#define CLK_CFG_1_SET		0x0024
#define CLK_CFG_1_CLR		0x0028
#define CLK_CFG_2		0x0030
#define CLK_CFG_2_SET		0x0034
#define CLK_CFG_2_CLR		0x0038
#define CLK_CFG_3		0x0040
#define CLK_CFG_3_SET		0x0044
#define CLK_CFG_3_CLR		0x0048
#define CLK_CFG_4		0x0050
#define CLK_CFG_4_SET		0x0054
#define CLK_CFG_4_CLR		0x0058
#define CLK_CFG_5		0x0060
#define CLK_CFG_5_SET		0x0064
#define CLK_CFG_5_CLR		0x0068
#define CLK_CFG_6		0x0070
#define CLK_CFG_6_SET		0x0074
#define CLK_CFG_6_CLR		0x0078
#define CLK_CFG_7		0x0080
#define CLK_CFG_7_SET		0x0084
#define CLK_CFG_7_CLR		0x0088
#define CLK_CFG_8		0x0090
#define CLK_CFG_8_SET		0x0094
#define CLK_CFG_8_CLR		0x0098
#define CLK_CFG_9		0x00a0
#define CLK_CFG_9_SET		0x00a4
#define CLK_CFG_9_CLR		0x00a8
#define CLK_CFG_10		0x00b0
#define CLK_CFG_10_SET		0x00b4
#define CLK_CFG_10_CLR		0x00b8
#define CLK_CFG_11		0x00c0
#define CLK_CFG_11_SET		0x00c4
#define CLK_CFG_11_CLR		0x00c8
#define CLK_CFG_12		0x00d0
#define CLK_CFG_12_SET		0x00d4
#define CLK_CFG_12_CLR		0x00d8
#define CLK_CFG_13		0x00e0
#define CLK_CFG_13_SET		0x00e4
#define CLK_CFG_13_CLR		0x00e8
#define CLK_CFG_14		0x00f0
#define CLK_CFG_14_SET		0x00f4
#define CLK_CFG_14_CLR		0x00f8
#define CLK_CFG_15		0x0100
#define CLK_CFG_15_SET		0x0104
#define CLK_CFG_15_CLR		0x0108
#define CLK_CFG_16		0x0110
#define CLK_CFG_16_SET		0x0114
#define CLK_CFG_16_CLR		0x0118
#define CLK_CFG_17		0x0120
#define CLK_CFG_17_SET		0x0124
#define CLK_CFG_17_CLR		0x0128
#define CLK_CFG_18		0x0130
#define CLK_CFG_18_SET		0x0134
#define CLK_CFG_18_CLR		0x0138
#define CLK_CFG_19		0x0140
#define CLK_CFG_19_SET		0x0144
#define CLK_CFG_19_CLR		0x0148
#define CLK_AUDDIV_0		0x020c
#define CLK_FENC_STATUS_MON_0	0x0270
#define CLK_FENC_STATUS_MON_1	0x0274
#define CLK_FENC_STATUS_MON_2	0x0278

/* MUX SHIFT */
#define TOP_MUX_AXI_SHIFT			0

Annotation

Implementation Notes