drivers/clk/mediatek/clk-mt8196-topckgen2.c

Source file repositories/reference/linux-study-clean/drivers/clk/mediatek/clk-mt8196-topckgen2.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/mediatek/clk-mt8196-topckgen2.c
Extension
.c
Size
17935 bytes
Lines
569
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2025 MediaTek Inc.
 *                    Guangjie Song <guangjie.song@mediatek.com>
 * Copyright (c) 2025 Collabora Ltd.
 *                    Laura Nao <laura.nao@collabora.com>
 */
#include <dt-bindings/clock/mediatek,mt8196-clock.h>

#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>

#include "clk-mtk.h"
#include "clk-mux.h"

/* MUX SEL REG */
#define CKSYS2_CLK_CFG_UPDATE		0x0004
#define CKSYS2_CLK_CFG_0		0x0010
#define CKSYS2_CLK_CFG_0_SET		0x0014
#define CKSYS2_CLK_CFG_0_CLR		0x0018
#define CKSYS2_CLK_CFG_1		0x0020
#define CKSYS2_CLK_CFG_1_SET		0x0024
#define CKSYS2_CLK_CFG_1_CLR		0x0028
#define CKSYS2_CLK_CFG_2		0x0030
#define CKSYS2_CLK_CFG_2_SET		0x0034
#define CKSYS2_CLK_CFG_2_CLR		0x0038
#define CKSYS2_CLK_CFG_3		0x0040
#define CKSYS2_CLK_CFG_3_SET		0x0044
#define CKSYS2_CLK_CFG_3_CLR		0x0048
#define CKSYS2_CLK_CFG_4		0x0050
#define CKSYS2_CLK_CFG_4_SET		0x0054
#define CKSYS2_CLK_CFG_4_CLR		0x0058
#define CKSYS2_CLK_CFG_5		0x0060
#define CKSYS2_CLK_CFG_5_SET		0x0064
#define CKSYS2_CLK_CFG_5_CLR		0x0068
#define CKSYS2_CLK_CFG_6		0x0070
#define CKSYS2_CLK_CFG_6_SET		0x0074
#define CKSYS2_CLK_CFG_6_CLR		0x0078
#define CKSYS2_CLK_FENC_STATUS_MON_0	0x0174

/* MUX SHIFT */
#define TOP_MUX_SENINF0_SHIFT		0
#define TOP_MUX_SENINF1_SHIFT		1
#define TOP_MUX_SENINF2_SHIFT		2
#define TOP_MUX_SENINF3_SHIFT		3
#define TOP_MUX_SENINF4_SHIFT		4
#define TOP_MUX_SENINF5_SHIFT		5
#define TOP_MUX_IMG1_SHIFT		6
#define TOP_MUX_IPE_SHIFT		7
#define TOP_MUX_CAM_SHIFT		8
#define TOP_MUX_CAMTM_SHIFT		9
#define TOP_MUX_DPE_SHIFT		10
#define TOP_MUX_VDEC_SHIFT		11
#define TOP_MUX_CCUSYS_SHIFT		12
#define TOP_MUX_CCUTM_SHIFT		13
#define TOP_MUX_VENC_SHIFT		14
#define TOP_MUX_DVO_SHIFT		15
#define TOP_MUX_DVO_FAVT_SHIFT		16
#define TOP_MUX_DP1_SHIFT		17
#define TOP_MUX_DP0_SHIFT		18
#define TOP_MUX_DISP_SHIFT		19
#define TOP_MUX_MDP_SHIFT		20
#define TOP_MUX_MMINFRA_SHIFT		21
#define TOP_MUX_MMINFRA_SNOC_SHIFT	22
#define TOP_MUX_MMUP_SHIFT		23
#define TOP_MUX_MMINFRA_AO_SHIFT	26

/* HW Voter REG */
#define HWV_CG_30_SET		0x0058
#define HWV_CG_30_CLR		0x005c
#define HWV_CG_30_DONE		0x2c2c

#define MM_HWV_CG_30_SET	0x00f0
#define MM_HWV_CG_30_CLR	0x00f4
#define MM_HWV_CG_30_DONE	0x2c78
#define MM_HWV_CG_31_SET	0x00f8
#define MM_HWV_CG_31_CLR	0x00fc
#define MM_HWV_CG_31_DONE	0x2c7c
#define MM_HWV_CG_32_SET	0x0100
#define MM_HWV_CG_32_CLR	0x0104
#define MM_HWV_CG_32_DONE	0x2c80
#define MM_HWV_CG_33_SET	0x0108
#define MM_HWV_CG_33_CLR	0x010c
#define MM_HWV_CG_33_DONE	0x2c84
#define MM_HWV_CG_34_SET	0x0110
#define MM_HWV_CG_34_CLR	0x0114

Annotation

Implementation Notes