drivers/clk/mediatek/clk-mt8196-venc.c

Source file repositories/reference/linux-study-clean/drivers/clk/mediatek/clk-mt8196-venc.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/mediatek/clk-mt8196-venc.c
Extension
.c
Size
6860 bytes
Lines
237
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2025 MediaTek Inc.
 *                    Guangjie Song <guangjie.song@mediatek.com>
 * Copyright (c) 2025 Collabora Ltd.
 *                    Laura Nao <laura.nao@collabora.com>
 */
#include <dt-bindings/clock/mediatek,mt8196-clock.h>

#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>

#include "clk-gate.h"
#include "clk-mtk.h"

static const struct mtk_gate_regs ven10_cg_regs = {
	.set_ofs = 0x4,
	.clr_ofs = 0x8,
	.sta_ofs = 0x0,
};

static const struct mtk_gate_regs ven10_hwv_regs = {
	.set_ofs = 0x00b8,
	.clr_ofs = 0x00bc,
	.sta_ofs = 0x2c5c,
};

static const struct mtk_gate_regs ven11_cg_regs = {
	.set_ofs = 0x10,
	.clr_ofs = 0x14,
	.sta_ofs = 0x10,
};

static const struct mtk_gate_regs ven11_hwv_regs = {
	.set_ofs = 0x00c0,
	.clr_ofs = 0x00c4,
	.sta_ofs = 0x2c60,
};

#define GATE_VEN10(_id, _name, _parent, _shift) {	\
		.id = _id,				\
		.name = _name,				\
		.parent_name = _parent,			\
		.regs = &ven10_cg_regs,			\
		.shift = _shift,			\
		.flags = CLK_OPS_PARENT_ENABLE,		\
		.ops = &mtk_clk_gate_ops_setclr_inv,	\
	}

#define GATE_HWV_VEN10_FLAGS(_id, _name, _parent, _shift, _flags) {	\
		.id = _id,						\
		.name = _name,						\
		.parent_name = _parent,					\
		.regs = &ven10_cg_regs,					\
		.hwv_regs = &ven10_hwv_regs,				\
		.shift = _shift,					\
		.ops = &mtk_clk_gate_hwv_ops_setclr_inv,		\
		.flags = (_flags) |					\
			 CLK_OPS_PARENT_ENABLE,				\
	}

#define GATE_HWV_VEN10(_id, _name, _parent, _shift)	\
	GATE_HWV_VEN10_FLAGS(_id, _name, _parent, _shift, 0)

#define GATE_HWV_VEN11(_id, _name, _parent, _shift) {	\
		.id = _id,				\
		.name = _name,				\
		.parent_name = _parent,			\
		.regs = &ven11_cg_regs,			\
		.hwv_regs = &ven11_hwv_regs,		\
		.shift = _shift,			\
		.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
		.flags = CLK_OPS_PARENT_ENABLE		\
	}

static const struct mtk_gate ven1_clks[] = {
	/* VEN10 */
	GATE_HWV_VEN10(CLK_VEN1_CKE0_LARB, "ven1_larb", "venc", 0),
	GATE_HWV_VEN10(CLK_VEN1_CKE1_VENC, "ven1_venc", "venc", 4),
	GATE_VEN10(CLK_VEN1_CKE2_JPGENC, "ven1_jpgenc", "venc", 8),
	GATE_VEN10(CLK_VEN1_CKE3_JPGDEC, "ven1_jpgdec", "venc", 12),
	GATE_VEN10(CLK_VEN1_CKE4_JPGDEC_C1, "ven1_jpgdec_c1", "venc", 16),
	GATE_HWV_VEN10(CLK_VEN1_CKE5_GALS, "ven1_gals", "venc", 28),
	GATE_HWV_VEN10(CLK_VEN1_CKE29_VENC_ADAB_CTRL, "ven1_venc_adab_ctrl",
			"venc", 29),
	GATE_HWV_VEN10_FLAGS(CLK_VEN1_CKE29_VENC_XPC_CTRL,
			      "ven1_venc_xpc_ctrl", "venc", 30,
			      CLK_IGNORE_UNUSED),

Annotation

Implementation Notes