drivers/clk/mediatek/clk-mt8196-vlpckgen.c

Source file repositories/reference/linux-study-clean/drivers/clk/mediatek/clk-mt8196-vlpckgen.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
Extension
.c
Size
21868 bytes
Lines
726
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2025 MediaTek Inc.
 *                    Guangjie Song <guangjie.song@mediatek.com>
 * Copyright (c) 2025 Collabora Ltd.
 *                    Laura Nao <laura.nao@collabora.com>
 */
#include <dt-bindings/clock/mediatek,mt8196-clock.h>

#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>

#include "clk-mtk.h"
#include "clk-mux.h"
#include "clk-pll.h"

/* MUX SEL REG */
#define VLP_CLK_CFG_UPDATE		0x0004
#define VLP_CLK_CFG_UPDATE1		0x0008
#define VLP_CLK_CFG_0			0x0010
#define VLP_CLK_CFG_0_SET		0x0014
#define VLP_CLK_CFG_0_CLR		0x0018
#define VLP_CLK_CFG_1			0x0020
#define VLP_CLK_CFG_1_SET		0x0024
#define VLP_CLK_CFG_1_CLR		0x0028
#define VLP_CLK_CFG_2			0x0030
#define VLP_CLK_CFG_2_SET		0x0034
#define VLP_CLK_CFG_2_CLR		0x0038
#define VLP_CLK_CFG_3			0x0040
#define VLP_CLK_CFG_3_SET		0x0044
#define VLP_CLK_CFG_3_CLR		0x0048
#define VLP_CLK_CFG_4			0x0050
#define VLP_CLK_CFG_4_SET		0x0054
#define VLP_CLK_CFG_4_CLR		0x0058
#define VLP_CLK_CFG_5			0x0060
#define VLP_CLK_CFG_5_SET		0x0064
#define VLP_CLK_CFG_5_CLR		0x0068
#define VLP_CLK_CFG_6			0x0070
#define VLP_CLK_CFG_6_SET		0x0074
#define VLP_CLK_CFG_6_CLR		0x0078
#define VLP_CLK_CFG_7			0x0080
#define VLP_CLK_CFG_7_SET		0x0084
#define VLP_CLK_CFG_7_CLR		0x0088
#define VLP_CLK_CFG_8			0x0090
#define VLP_CLK_CFG_8_SET		0x0094
#define VLP_CLK_CFG_8_CLR		0x0098
#define VLP_CLK_CFG_9			0x00a0
#define VLP_CLK_CFG_9_SET		0x00a4
#define VLP_CLK_CFG_9_CLR		0x00a8
#define VLP_CLK_CFG_10			0x00b0
#define VLP_CLK_CFG_10_SET		0x00b4
#define VLP_CLK_CFG_10_CLR		0x00b8
#define VLP_OCIC_FENC_STATUS_MON_0	0x039c
#define VLP_OCIC_FENC_STATUS_MON_1	0x03a0

/* MUX SHIFT */
#define TOP_MUX_SCP_SHIFT			0
#define TOP_MUX_SCP_SPI_SHIFT			1
#define TOP_MUX_SCP_IIC_SHIFT			2
#define TOP_MUX_SCP_IIC_HS_SHIFT		3
#define TOP_MUX_PWRAP_ULPOSC_SHIFT		4
#define TOP_MUX_SPMI_M_TIA_32K_SHIFT		5
#define TOP_MUX_APXGPT_26M_B_SHIFT		6
#define TOP_MUX_DPSW_SHIFT			7
#define TOP_MUX_DPSW_CENTRAL_SHIFT		8
#define TOP_MUX_SPMI_M_MST_SHIFT		9
#define TOP_MUX_DVFSRC_SHIFT			10
#define TOP_MUX_PWM_VLP_SHIFT			11
#define TOP_MUX_AXI_VLP_SHIFT			12
#define TOP_MUX_SYSTIMER_26M_SHIFT		13
#define TOP_MUX_SSPM_SHIFT			14
#define TOP_MUX_SRCK_SHIFT			15
#define TOP_MUX_CAMTG0_SHIFT			16
#define TOP_MUX_CAMTG1_SHIFT			17
#define TOP_MUX_CAMTG2_SHIFT			18
#define TOP_MUX_CAMTG3_SHIFT			19
#define TOP_MUX_CAMTG4_SHIFT			20
#define TOP_MUX_CAMTG5_SHIFT			21
#define TOP_MUX_CAMTG6_SHIFT			22
#define TOP_MUX_CAMTG7_SHIFT			23
#define TOP_MUX_SSPM_26M_SHIFT			25
#define TOP_MUX_ULPOSC_SSPM_SHIFT		26
#define TOP_MUX_VLP_PBUS_26M_SHIFT		27
#define TOP_MUX_DEBUG_ERR_FLAG_VLP_26M_SHIFT	28
#define TOP_MUX_DPMSRDMA_SHIFT			29

Annotation

Implementation Notes