drivers/clk/meson/a1-peripherals.c

Source file repositories/reference/linux-study-clean/drivers/clk/meson/a1-peripherals.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/meson/a1-peripherals.c
Extension
.c
Size
51975 bytes
Lines
2101
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 * Author: Jian Hu <jian.hu@amlogic.com>
 *
 * Copyright (c) 2023, SberDevices. All Rights Reserved.
 * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
 */

#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-dualdiv.h"
#include "clk-regmap.h"
#include "meson-clkc-utils.h"

#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>

#define SYS_OSCIN_CTRL		0x0
#define RTC_BY_OSCIN_CTRL0	0x4
#define RTC_BY_OSCIN_CTRL1	0x8
#define RTC_CTRL		0xc
#define SYS_CLK_CTRL0		0x10
#define SYS_CLK_EN0		0x1c
#define SYS_CLK_EN1		0x20
#define AXI_CLK_EN		0x24
#define DSPA_CLK_EN		0x28
#define DSPB_CLK_EN		0x2c
#define DSPA_CLK_CTRL0		0x30
#define DSPB_CLK_CTRL0		0x34
#define CLK12_24_CTRL		0x38
#define GEN_CLK_CTRL		0x3c
#define SAR_ADC_CLK_CTRL	0xc0
#define PWM_CLK_AB_CTRL		0xc4
#define PWM_CLK_CD_CTRL		0xc8
#define PWM_CLK_EF_CTRL		0xcc
#define SPICC_CLK_CTRL		0xd0
#define TS_CLK_CTRL		0xd4
#define SPIFC_CLK_CTRL		0xd8
#define USB_BUSCLK_CTRL		0xdc
#define SD_EMMC_CLK_CTRL	0xe0
#define CECA_CLK_CTRL0		0xe4
#define CECA_CLK_CTRL1		0xe8
#define CECB_CLK_CTRL0		0xec
#define CECB_CLK_CTRL1		0xf0
#define PSRAM_CLK_CTRL		0xf4
#define DMC_CLK_CTRL		0xf8

static struct clk_regmap a1_xtal_in = {
	.data = &(struct clk_regmap_gate_data){
		.offset = SYS_OSCIN_CTRL,
		.bit_idx = 0,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "xtal_in",
		.ops = &clk_regmap_gate_ro_ops,
		.parent_data = &(const struct clk_parent_data) {
			.fw_name = "xtal",
		},
		.num_parents = 1,
	},
};

static struct clk_regmap a1_fixpll_in = {
	.data = &(struct clk_regmap_gate_data){
		.offset = SYS_OSCIN_CTRL,
		.bit_idx = 1,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "fixpll_in",
		.ops = &clk_regmap_gate_ro_ops,
		.parent_data = &(const struct clk_parent_data) {
			.fw_name = "xtal",
		},
		.num_parents = 1,
	},
};

static struct clk_regmap a1_usb_phy_in = {
	.data = &(struct clk_regmap_gate_data){
		.offset = SYS_OSCIN_CTRL,
		.bit_idx = 2,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "usb_phy_in",
		.ops = &clk_regmap_gate_ops,
		.parent_data = &(const struct clk_parent_data) {
			.fw_name = "xtal",
		},
		.num_parents = 1,

Annotation

Implementation Notes