drivers/clk/meson/a1-pll.c

Source file repositories/reference/linux-study-clean/drivers/clk/meson/a1-pll.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/meson/a1-pll.c
Extension
.c
Size
7869 bytes
Lines
328
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 * Author: Jian Hu <jian.hu@amlogic.com>
 *
 * Copyright (c) 2023, SberDevices. All Rights Reserved.
 * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
 */

#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-pll.h"
#include "clk-regmap.h"
#include "meson-clkc-utils.h"

#define ANACTRL_FIXPLL_CTRL0	0x0
#define ANACTRL_FIXPLL_CTRL1	0x4
#define ANACTRL_FIXPLL_STS	0x14
#define ANACTRL_HIFIPLL_CTRL0	0xc0
#define ANACTRL_HIFIPLL_CTRL1	0xc4
#define ANACTRL_HIFIPLL_CTRL2	0xc8
#define ANACTRL_HIFIPLL_CTRL3	0xcc
#define ANACTRL_HIFIPLL_CTRL4	0xd0
#define ANACTRL_HIFIPLL_STS	0xd4

#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>

static struct clk_regmap a1_fixed_pll_dco = {
	.data = &(struct meson_clk_pll_data){
		.en = {
			.reg_off = ANACTRL_FIXPLL_CTRL0,
			.shift   = 28,
			.width   = 1,
		},
		.m = {
			.reg_off = ANACTRL_FIXPLL_CTRL0,
			.shift   = 0,
			.width   = 8,
		},
		.n = {
			.reg_off = ANACTRL_FIXPLL_CTRL0,
			.shift   = 10,
			.width   = 5,
		},
		.frac = {
			.reg_off = ANACTRL_FIXPLL_CTRL1,
			.shift   = 0,
			.width   = 19,
		},
		.l = {
			.reg_off = ANACTRL_FIXPLL_STS,
			.shift   = 31,
			.width   = 1,
		},
		.rst = {
			.reg_off = ANACTRL_FIXPLL_CTRL0,
			.shift   = 29,
			.width   = 1,
		},
	},
	.hw.init = &(struct clk_init_data){
		.name = "fixed_pll_dco",
		.ops = &meson_clk_pll_ro_ops,
		.parent_data = &(const struct clk_parent_data) {
			.fw_name = "fixpll_in",
		},
		.num_parents = 1,
	},
};

static struct clk_regmap a1_fixed_pll = {
	.data = &(struct clk_regmap_gate_data){
		.offset = ANACTRL_FIXPLL_CTRL0,
		.bit_idx = 20,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "fixed_pll",
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
			&a1_fixed_pll_dco.hw
		},
		.num_parents = 1,
	},
};

static const struct pll_mult_range a1_hifi_pll_range = {
	.min = 32,
	.max = 64,
};

Annotation

Implementation Notes