drivers/clk/meson/axg-aoclk.c

Source file repositories/reference/linux-study-clean/drivers/clk/meson/axg-aoclk.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/meson/axg-aoclk.c
Extension
.c
Size
8044 bytes
Lines
321
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * Amlogic Meson-AXG Clock Controller Driver
 *
 * Copyright (c) 2016 Baylibre SAS.
 * Author: Michael Turquette <mturquette@baylibre.com>
 *
 * Copyright (c) 2018 Amlogic, inc.
 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
 */
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include "meson-aoclk.h"

#include "clk-regmap.h"
#include "clk-dualdiv.h"

#include <dt-bindings/clock/axg-aoclkc.h>
#include <dt-bindings/reset/axg-aoclkc.h>

/*
 * AO Configuration Clock registers offsets
 * Register offsets from the data sheet must be multiplied by 4.
 */
#define AO_RTI_PWR_CNTL_REG1	0x0C
#define AO_RTI_PWR_CNTL_REG0	0x10
#define AO_RTI_GEN_CNTL_REG0	0x40
#define AO_OSCIN_CNTL		0x58
#define AO_CRT_CLK_CNTL1	0x68
#define AO_SAR_CLK		0x90
#define AO_RTC_ALT_CLK_CNTL0	0x94
#define AO_RTC_ALT_CLK_CNTL1	0x98

static const struct clk_parent_data axg_ao_pclk_parents = { .fw_name = "mpeg-clk" };

#define AXG_AO_GATE(_name, _bit, _flags)		       \
	MESON_PCLK(axg_ao_##_name, AO_RTI_GEN_CNTL_REG0, _bit, \
		   &axg_ao_pclk_parents, _flags)

static AXG_AO_GATE(remote,	0, CLK_IGNORE_UNUSED);
static AXG_AO_GATE(i2c_master,	1, CLK_IGNORE_UNUSED);
static AXG_AO_GATE(i2c_slave,	2, CLK_IGNORE_UNUSED);
static AXG_AO_GATE(uart1,	3, CLK_IGNORE_UNUSED);
static AXG_AO_GATE(uart2,	5, CLK_IGNORE_UNUSED);
static AXG_AO_GATE(ir_blaster,	6, CLK_IGNORE_UNUSED);
static AXG_AO_GATE(saradc,	7, CLK_IGNORE_UNUSED);

static struct clk_regmap axg_ao_cts_oscin = {
	.data = &(struct clk_regmap_gate_data){
		.offset = AO_RTI_PWR_CNTL_REG0,
		.bit_idx = 14,
	},
	.hw.init = &(struct clk_init_data){
		.name = "cts_oscin",
		.ops = &clk_regmap_gate_ro_ops,
		.parent_data = &(const struct clk_parent_data) {
			.fw_name = "xtal",
		},
		.num_parents = 1,
	},
};

static struct clk_regmap axg_ao_32k_pre = {
	.data = &(struct clk_regmap_gate_data){
		.offset = AO_RTC_ALT_CLK_CNTL0,
		.bit_idx = 31,
	},
	.hw.init = &(struct clk_init_data){
		.name = "axg_ao_32k_pre",
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
			&axg_ao_cts_oscin.hw
		},
		.num_parents = 1,
	},
};

static const struct meson_clk_dualdiv_param axg_32k_div_table[] = {
	{
		.dual	= 1,
		.n1	= 733,
		.m1	= 8,
		.n2	= 732,
		.m2	= 11,
	}, {}
};

Annotation

Implementation Notes