drivers/clk/meson/c3-pll.c

Source file repositories/reference/linux-study-clean/drivers/clk/meson/c3-pll.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/meson/c3-pll.c
Extension
.c
Size
16206 bytes
Lines
685
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Amlogic C3 PLL Controller Driver
 *
 * Copyright (c) 2023 Amlogic, inc.
 * Author: Chuan Liu <chuan.liu@amlogic.com>
 */

#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-regmap.h"
#include "clk-pll.h"
#include "meson-clkc-utils.h"
#include <dt-bindings/clock/amlogic,c3-pll-clkc.h>

#define ANACTRL_FIXPLL_CTRL4			0x50
#define ANACTRL_GP0PLL_CTRL0			0x80
#define ANACTRL_GP0PLL_CTRL1			0x84
#define ANACTRL_GP0PLL_CTRL2			0x88
#define ANACTRL_GP0PLL_CTRL3			0x8c
#define ANACTRL_GP0PLL_CTRL4			0x90
#define ANACTRL_GP0PLL_CTRL5			0x94
#define ANACTRL_GP0PLL_CTRL6			0x98
#define ANACTRL_HIFIPLL_CTRL0			0x100
#define ANACTRL_HIFIPLL_CTRL1			0x104
#define ANACTRL_HIFIPLL_CTRL2			0x108
#define ANACTRL_HIFIPLL_CTRL3			0x10c
#define ANACTRL_HIFIPLL_CTRL4			0x110
#define ANACTRL_HIFIPLL_CTRL5			0x114
#define ANACTRL_HIFIPLL_CTRL6			0x118
#define ANACTRL_MPLL_CTRL0			0x180
#define ANACTRL_MPLL_CTRL1			0x184
#define ANACTRL_MPLL_CTRL2			0x188
#define ANACTRL_MPLL_CTRL3			0x18c
#define ANACTRL_MPLL_CTRL4			0x190

static struct clk_regmap c3_fclk_50m_en = {
	.data = &(struct clk_regmap_gate_data) {
		.offset = ANACTRL_FIXPLL_CTRL4,
		.bit_idx = 0,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "fclk_50m_en",
		.ops = &clk_regmap_gate_ro_ops,
		.parent_data = &(const struct clk_parent_data) {
			.fw_name = "fix"
		},
		.num_parents = 1,
	},
};

static struct clk_fixed_factor c3_fclk_50m = {
	.mult = 1,
	.div = 40,
	.hw.init = &(struct clk_init_data) {
		.name = "fclk_50m",
		.ops = &clk_fixed_factor_ops,
		.parent_hws = (const struct clk_hw *[]) {
			&c3_fclk_50m_en.hw
		},
		.num_parents = 1,
	},
};

static struct clk_fixed_factor c3_fclk_div2_div = {
	.mult = 1,
	.div = 2,
	.hw.init = &(struct clk_init_data) {
		.name = "fclk_div2_div",
		.ops = &clk_fixed_factor_ops,
		.parent_data = &(const struct clk_parent_data) {
			.fw_name = "fix"
		},
		.num_parents = 1,
	},
};

static struct clk_regmap c3_fclk_div2 = {
	.data = &(struct clk_regmap_gate_data) {
		.offset = ANACTRL_FIXPLL_CTRL4,
		.bit_idx = 24,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "fclk_div2",
		.ops = &clk_regmap_gate_ro_ops,
		.parent_hws = (const struct clk_hw *[]) {
			&c3_fclk_div2_div.hw
		},
		.num_parents = 1,
	},

Annotation

Implementation Notes