drivers/clk/meson/gxbb.c

Source file repositories/reference/linux-study-clean/drivers/clk/meson/gxbb.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/meson/gxbb.c
Extension
.c
Size
91670 bytes
Lines
3299
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2016 AmLogic, Inc.
 * Michael Turquette <mturquette@baylibre.com>
 */

#include <linux/clk-provider.h>
#include <linux/init.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/module.h>

#include "clk-regmap.h"
#include "clk-pll.h"
#include "clk-mpll.h"
#include "meson-clkc-utils.h"
#include "vid-pll-div.h"

#include <dt-bindings/clock/gxbb-clkc.h>

#define SCR				0x2c
#define TIMEOUT_VALUE			0x3c

#define HHI_GP0_PLL_CNTL		0x40
#define HHI_GP0_PLL_CNTL2		0x44
#define HHI_GP0_PLL_CNTL3		0x48
#define HHI_GP0_PLL_CNTL4		0x4c
#define	HHI_GP0_PLL_CNTL5		0x50
#define	HHI_GP0_PLL_CNTL1		0x58

#define HHI_XTAL_DIVN_CNTL		0xbc
#define HHI_TIMER90K			0xec

#define HHI_MEM_PD_REG0			0x100
#define HHI_MEM_PD_REG1			0x104
#define HHI_VPU_MEM_PD_REG1		0x108
#define HHI_VIID_CLK_DIV		0x128
#define HHI_VIID_CLK_CNTL		0x12c

#define HHI_GCLK_MPEG0			0x140
#define HHI_GCLK_MPEG1			0x144
#define HHI_GCLK_MPEG2			0x148
#define HHI_GCLK_OTHER			0x150
#define HHI_GCLK_AO			0x154
#define HHI_SYS_OSCIN_CNTL		0x158
#define HHI_SYS_CPU_CLK_CNTL1		0x15c
#define HHI_SYS_CPU_RESET_CNTL		0x160
#define HHI_VID_CLK_DIV			0x164

#define HHI_MPEG_CLK_CNTL		0x174
#define HHI_AUD_CLK_CNTL		0x178
#define HHI_VID_CLK_CNTL		0x17c
#define HHI_AUD_CLK_CNTL2		0x190
#define HHI_VID_CLK_CNTL2		0x194
#define HHI_SYS_CPU_CLK_CNTL0		0x19c
#define HHI_VID_PLL_CLK_DIV		0x1a0
#define HHI_AUD_CLK_CNTL3		0x1a4
#define HHI_MALI_CLK_CNTL		0x1b0
#define HHI_VPU_CLK_CNTL		0x1bc

#define HHI_HDMI_CLK_CNTL		0x1cc
#define HHI_VDEC_CLK_CNTL		0x1e0
#define HHI_VDEC2_CLK_CNTL		0x1e4
#define HHI_VDEC3_CLK_CNTL		0x1e8
#define HHI_VDEC4_CLK_CNTL		0x1ec
#define HHI_HDCP22_CLK_CNTL		0x1f0
#define HHI_VAPBCLK_CNTL		0x1f4

#define HHI_VPU_CLKB_CNTL		0x20c
#define HHI_USB_CLK_CNTL		0x220
#define HHI_32K_CLK_CNTL		0x224
#define HHI_GEN_CLK_CNTL		0x228

#define HHI_PCM_CLK_CNTL		0x258
#define HHI_NAND_CLK_CNTL		0x25c
#define HHI_SD_EMMC_CLK_CNTL		0x264

#define HHI_MPLL_CNTL			0x280
#define HHI_MPLL_CNTL2			0x284
#define HHI_MPLL_CNTL3			0x288
#define HHI_MPLL_CNTL4			0x28c
#define HHI_MPLL_CNTL5			0x290
#define HHI_MPLL_CNTL6			0x294
#define HHI_MPLL_CNTL7			0x298
#define HHI_MPLL_CNTL8			0x29c
#define HHI_MPLL_CNTL9			0x2a0
#define HHI_MPLL_CNTL10			0x2a4

#define HHI_MPLL3_CNTL0			0x2e0
#define HHI_MPLL3_CNTL1			0x2e4

Annotation

Implementation Notes