drivers/clk/meson/s4-peripherals.c

Source file repositories/reference/linux-study-clean/drivers/clk/meson/s4-peripherals.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/meson/s4-peripherals.c
Extension
.c
Size
86292 bytes
Lines
3260
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
/*
 * Amlogic S4 Peripherals Clock Controller Driver
 *
 * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved
 * Author: Yu Tu <yu.tu@amlogic.com>
 */

#include <linux/clk-provider.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>

#include "clk-regmap.h"
#include "vid-pll-div.h"
#include "clk-dualdiv.h"
#include "meson-clkc-utils.h"
#include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>

#define CLKCTRL_RTC_BY_OSCIN_CTRL0                 0x008
#define CLKCTRL_RTC_BY_OSCIN_CTRL1                 0x00c
#define CLKCTRL_RTC_CTRL                           0x010
#define CLKCTRL_SYS_CLK_CTRL0                      0x040
#define CLKCTRL_SYS_CLK_EN0_REG0                   0x044
#define CLKCTRL_SYS_CLK_EN0_REG1                   0x048
#define CLKCTRL_SYS_CLK_EN0_REG2                   0x04c
#define CLKCTRL_SYS_CLK_EN0_REG3                   0x050
#define CLKCTRL_CECA_CTRL0                         0x088
#define CLKCTRL_CECA_CTRL1                         0x08c
#define CLKCTRL_CECB_CTRL0                         0x090
#define CLKCTRL_CECB_CTRL1                         0x094
#define CLKCTRL_SC_CLK_CTRL                        0x098
#define CLKCTRL_CLK12_24_CTRL                      0x0a8
#define CLKCTRL_VID_CLK_CTRL                       0x0c0
#define CLKCTRL_VID_CLK_CTRL2                      0x0c4
#define CLKCTRL_VID_CLK_DIV                        0x0c8
#define CLKCTRL_VIID_CLK_DIV                       0x0cc
#define CLKCTRL_VIID_CLK_CTRL                      0x0d0
#define CLKCTRL_HDMI_CLK_CTRL                      0x0e0
#define CLKCTRL_VID_PLL_CLK_DIV                    0x0e4
#define CLKCTRL_VPU_CLK_CTRL                       0x0e8
#define CLKCTRL_VPU_CLKB_CTRL                      0x0ec
#define CLKCTRL_VPU_CLKC_CTRL                      0x0f0
#define CLKCTRL_VID_LOCK_CLK_CTRL                  0x0f4
#define CLKCTRL_VDIN_MEAS_CLK_CTRL                 0x0f8
#define CLKCTRL_VAPBCLK_CTRL                       0x0fc
#define CLKCTRL_HDCP22_CTRL                        0x100
#define CLKCTRL_CDAC_CLK_CTRL                      0x108
#define CLKCTRL_VDEC_CLK_CTRL                      0x140
#define CLKCTRL_VDEC2_CLK_CTRL                     0x144
#define CLKCTRL_VDEC3_CLK_CTRL                     0x148
#define CLKCTRL_VDEC4_CLK_CTRL                     0x14c
#define CLKCTRL_TS_CLK_CTRL                        0x158
#define CLKCTRL_MALI_CLK_CTRL                      0x15c
#define CLKCTRL_NAND_CLK_CTRL                      0x168
#define CLKCTRL_SD_EMMC_CLK_CTRL                   0x16c
#define CLKCTRL_SPICC_CLK_CTRL                     0x174
#define CLKCTRL_GEN_CLK_CTRL                       0x178
#define CLKCTRL_SAR_CLK_CTRL                       0x17c
#define CLKCTRL_PWM_CLK_AB_CTRL                    0x180
#define CLKCTRL_PWM_CLK_CD_CTRL                    0x184
#define CLKCTRL_PWM_CLK_EF_CTRL                    0x188
#define CLKCTRL_PWM_CLK_GH_CTRL                    0x18c
#define CLKCTRL_PWM_CLK_IJ_CTRL                    0x190
#define CLKCTRL_DEMOD_CLK_CTRL                     0x200

#define S4_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \
	MESON_COMP_SEL(s4_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0)

#define S4_COMP_DIV(_name, _reg, _shift, _width) \
	MESON_COMP_DIV(s4_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT)

#define S4_COMP_GATE(_name, _reg, _bit) \
	MESON_COMP_GATE(s4_, _name, _reg, _bit, CLK_SET_RATE_PARENT)

static struct clk_regmap s4_rtc_32k_by_oscin_clkin = {
	.data = &(struct clk_regmap_gate_data){
		.offset = CLKCTRL_RTC_BY_OSCIN_CTRL0,
		.bit_idx = 31,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "rtc_32k_by_oscin_clkin",
		.ops = &clk_regmap_gate_ops,
		.parent_data = (const struct clk_parent_data []) {
			{ .fw_name = "xtal", }
		},
		.num_parents = 1,
	},
};

static const struct meson_clk_dualdiv_param s4_32k_div_table[] = {

Annotation

Implementation Notes