drivers/clk/meson/s4-pll.c

Source file repositories/reference/linux-study-clean/drivers/clk/meson/s4-pll.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/meson/s4-pll.c
Extension
.c
Size
20415 bytes
Lines
832
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
/*
 * Amlogic S4 PLL Clock Controller Driver
 *
 * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved
 * Author: Yu Tu <yu.tu@amlogic.com>
 */

#include <linux/clk-provider.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>

#include "clk-mpll.h"
#include "clk-pll.h"
#include "clk-regmap.h"
#include "meson-clkc-utils.h"
#include <dt-bindings/clock/amlogic,s4-pll-clkc.h>

#define ANACTRL_FIXPLL_CTRL0                       0x040
#define ANACTRL_FIXPLL_CTRL1                       0x044
#define ANACTRL_FIXPLL_CTRL3                       0x04c
#define ANACTRL_GP0PLL_CTRL0                       0x080
#define ANACTRL_GP0PLL_CTRL1                       0x084
#define ANACTRL_GP0PLL_CTRL2                       0x088
#define ANACTRL_GP0PLL_CTRL3                       0x08c
#define ANACTRL_GP0PLL_CTRL4                       0x090
#define ANACTRL_GP0PLL_CTRL5                       0x094
#define ANACTRL_GP0PLL_CTRL6                       0x098
#define ANACTRL_HIFIPLL_CTRL0                      0x100
#define ANACTRL_HIFIPLL_CTRL1                      0x104
#define ANACTRL_HIFIPLL_CTRL2                      0x108
#define ANACTRL_HIFIPLL_CTRL3                      0x10c
#define ANACTRL_HIFIPLL_CTRL4                      0x110
#define ANACTRL_HIFIPLL_CTRL5                      0x114
#define ANACTRL_HIFIPLL_CTRL6                      0x118
#define ANACTRL_MPLL_CTRL0                         0x180
#define ANACTRL_MPLL_CTRL1                         0x184
#define ANACTRL_MPLL_CTRL2                         0x188
#define ANACTRL_MPLL_CTRL3                         0x18c
#define ANACTRL_MPLL_CTRL4                         0x190
#define ANACTRL_MPLL_CTRL5                         0x194
#define ANACTRL_MPLL_CTRL6                         0x198
#define ANACTRL_MPLL_CTRL7                         0x19c
#define ANACTRL_MPLL_CTRL8                         0x1a0
#define ANACTRL_HDMIPLL_CTRL0                      0x1c0

/*
 * These clock are a fixed value (fixed_pll is 2GHz) that is initialized by ROMcode.
 * The chip was changed fixed pll for security reasons. Fixed PLL registers are not writable
 * in the kernel phase. Write of fixed PLL-related register will cause the system to crash.
 * Meanwhile, these clock won't ever change at runtime.
 * For the above reasons, we can only use ro_ops for fixed PLL related clocks.
 */
static struct clk_regmap s4_fixed_pll_dco = {
	.data = &(struct meson_clk_pll_data){
		.en = {
			.reg_off = ANACTRL_FIXPLL_CTRL0,
			.shift   = 28,
			.width   = 1,
		},
		.m = {
			.reg_off = ANACTRL_FIXPLL_CTRL0,
			.shift   = 0,
			.width   = 8,
		},
		.frac = {
			.reg_off = ANACTRL_FIXPLL_CTRL1,
			.shift   = 0,
			.width   = 17,
		},
		.n = {
			.reg_off = ANACTRL_FIXPLL_CTRL0,
			.shift   = 10,
			.width   = 5,
		},
		.l = {
			.reg_off = ANACTRL_FIXPLL_CTRL0,
			.shift   = 31,
			.width   = 1,
		},
		.rst = {
			.reg_off = ANACTRL_FIXPLL_CTRL0,
			.shift   = 29,
			.width   = 1,
		},
	},
	.hw.init = &(struct clk_init_data){
		.name = "fixed_pll_dco",
		.ops = &meson_clk_pll_ro_ops,
		.parent_data = (const struct clk_parent_data []) {

Annotation

Implementation Notes