drivers/clk/meson/vclk.c

Source file repositories/reference/linux-study-clean/drivers/clk/meson/vclk.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/meson/vclk.c
Extension
.c
Size
4110 bytes
Lines
145
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2024 Neil Armstrong <neil.armstrong@linaro.org>
 */

#include <linux/module.h>
#include "vclk.h"

/* The VCLK gate has a supplementary reset bit to pulse after ungating */

static inline struct meson_vclk_gate_data *
clk_get_meson_vclk_gate_data(struct clk_regmap *clk)
{
	return (struct meson_vclk_gate_data *)clk->data;
}

static int meson_vclk_gate_enable(struct clk_hw *hw)
{
	struct clk_regmap *clk = to_clk_regmap(hw);
	struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);

	meson_parm_write(clk->map, &vclk->enable, 1);

	/* Do a reset pulse */
	meson_parm_write(clk->map, &vclk->reset, 1);
	meson_parm_write(clk->map, &vclk->reset, 0);

	return 0;
}

static void meson_vclk_gate_disable(struct clk_hw *hw)
{
	struct clk_regmap *clk = to_clk_regmap(hw);
	struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);

	meson_parm_write(clk->map, &vclk->enable, 0);
}

static int meson_vclk_gate_is_enabled(struct clk_hw *hw)
{
	struct clk_regmap *clk = to_clk_regmap(hw);
	struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);

	return meson_parm_read(clk->map, &vclk->enable);
}

const struct clk_ops meson_vclk_gate_ops = {
	.init = clk_regmap_init,
	.enable = meson_vclk_gate_enable,
	.disable = meson_vclk_gate_disable,
	.is_enabled = meson_vclk_gate_is_enabled,
};
EXPORT_SYMBOL_NS_GPL(meson_vclk_gate_ops, "CLK_MESON");

/* The VCLK Divider has supplementary reset & enable bits */

static inline struct meson_vclk_div_data *
clk_get_meson_vclk_div_data(struct clk_regmap *clk)
{
	return (struct meson_vclk_div_data *)clk->data;
}

static unsigned long meson_vclk_div_recalc_rate(struct clk_hw *hw,
						unsigned long prate)
{
	struct clk_regmap *clk = to_clk_regmap(hw);
	struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);

	return divider_recalc_rate(hw, prate, meson_parm_read(clk->map, &vclk->div),
				   vclk->table, vclk->flags, vclk->div.width);
}

static int meson_vclk_div_determine_rate(struct clk_hw *hw,
					 struct clk_rate_request *req)
{
	struct clk_regmap *clk = to_clk_regmap(hw);
	struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);

	return divider_determine_rate(hw, req, vclk->table, vclk->div.width,
				      vclk->flags);
}

static int meson_vclk_div_set_rate(struct clk_hw *hw, unsigned long rate,
				   unsigned long parent_rate)
{
	struct clk_regmap *clk = to_clk_regmap(hw);
	struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
	int ret;

	ret = divider_get_val(rate, parent_rate, vclk->table, vclk->div.width,

Annotation

Implementation Notes