drivers/clk/mmp/clk-of-mmp2.c

Source file repositories/reference/linux-study-clean/drivers/clk/mmp/clk-of-mmp2.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/mmp/clk-of-mmp2.c
Extension
.c
Size
23593 bytes
Lines
570
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct mmp2_clk_unit {
	struct mmp_clk_unit unit;
	enum mmp2_clk_model model;
	struct genpd_onecell_data pd_data;
	struct generic_pm_domain *pm_domains[MMP2_NR_POWER_DOMAINS];
	void __iomem *mpmu_base;
	void __iomem *apmu_base;
	void __iomem *apbc_base;
};

static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
	{MMP2_CLK_CLK32, "clk32", NULL, 0, 32768},
	{MMP2_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000},
	{MMP2_CLK_USB_PLL, "usb_pll", NULL, 0, 480000000},
	{0, "i2s_pll", NULL, 0, 99666667},
};

static struct mmp_param_pll_clk pll_clks[] = {
	{MMP2_CLK_PLL1,   "pll1",   797330000, MPMU_FCCR,          0x4000, MPMU_POSR,     0},
	{MMP2_CLK_PLL2,   "pll2",           0, MPMU_PLL2_CR,       0x0300, MPMU_PLL2_CR, 10},
};

static struct mmp_param_pll_clk mmp3_pll_clks[] = {
	{MMP2_CLK_PLL2,   "pll1",   797330000, MPMU_FCCR,          0x4000, MPMU_POSR,     0,      26000000, MPMU_PLL1_CTRL,      25},
	{MMP2_CLK_PLL2,   "pll2",           0, MPMU_PLL2_CR,       0x0300, MPMU_PLL2_CR, 10,      26000000, MPMU_PLL2_CTRL1,     25},
	{MMP3_CLK_PLL1_P, "pll1_p",         0, MPMU_PLL_DIFF_CTRL, 0x0010, 0,             0,     797330000, MPMU_PLL_DIFF_CTRL,   0},
	{MMP3_CLK_PLL2_P, "pll2_p",         0, MPMU_PLL_DIFF_CTRL, 0x0100, MPMU_PLL2_CR, 10,      26000000, MPMU_PLL_DIFF_CTRL,   5},
	{MMP3_CLK_PLL3,   "pll3",           0, MPMU_PLL3_CR,       0x0300, MPMU_PLL3_CR, 10,      26000000, MPMU_PLL3_CTRL1,     25},
};

static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
	{MMP2_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
	{MMP2_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
	{MMP2_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
	{MMP2_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
	{MMP2_CLK_PLL1_20, "pll1_20", "pll1_4", 1, 5, 0},
	{MMP2_CLK_PLL1_3, "pll1_3", "pll1", 1, 3, 0},
	{MMP2_CLK_PLL1_6, "pll1_6", "pll1_3", 1, 2, 0},
	{MMP2_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
	{MMP2_CLK_PLL2_2, "pll2_2", "pll2", 1, 2, 0},
	{MMP2_CLK_PLL2_4, "pll2_4", "pll2_2", 1, 2, 0},
	{MMP2_CLK_PLL2_8, "pll2_8", "pll2_4", 1, 2, 0},
	{MMP2_CLK_PLL2_16, "pll2_16", "pll2_8", 1, 2, 0},
	{MMP2_CLK_PLL2_3, "pll2_3", "pll2", 1, 3, 0},
	{MMP2_CLK_PLL2_6, "pll2_6", "pll2_3", 1, 2, 0},
	{MMP2_CLK_PLL2_12, "pll2_12", "pll2_6", 1, 2, 0},
	{MMP2_CLK_VCTCXO_2, "vctcxo_2", "vctcxo", 1, 2, 0},
	{MMP2_CLK_VCTCXO_4, "vctcxo_4", "vctcxo_2", 1, 2, 0},
};

static struct mmp_clk_factor_masks uart_factor_masks = {
	.factor = 2,
	.num_mask = 0x1fff,
	.den_mask = 0x1fff,
	.num_shift = 16,
	.den_shift = 0,
};

static struct u32_fract uart_factor_tbl[] = {
	{ .numerator = 8125, .denominator = 1536 },	/* 14.745MHZ */
	{ .numerator = 3521, .denominator =  689 },	/* 19.23MHZ */
};

static struct mmp_clk_factor_masks i2s_factor_masks = {
	.factor = 2,
	.num_mask = 0x7fff,
	.den_mask = 0x1fff,
	.num_shift = 0,
	.den_shift = 15,
	.enable_mask = 0xd0000000,
};

static struct u32_fract i2s_factor_tbl[] = {
	{ .numerator = 24868, .denominator =  511 },	/*  2.0480 MHz */
	{ .numerator = 28003, .denominator =  793 },	/*  2.8224 MHz */
	{ .numerator = 24941, .denominator = 1025 },	/*  4.0960 MHz */
	{ .numerator = 28003, .denominator = 1586 },	/*  5.6448 MHz */
	{ .numerator = 31158, .denominator = 2561 },	/*  8.1920 MHz */
	{ .numerator = 16288, .denominator = 1845 },	/* 11.2896 MHz */
	{ .numerator = 20772, .denominator = 2561 },	/* 12.2880 MHz */
	{ .numerator =  8144, .denominator = 1845 },	/* 22.5792 MHz */
	{ .numerator = 10386, .denominator = 2561 },	/* 24.5760 MHz */
};

static DEFINE_SPINLOCK(acgr_lock);

static struct mmp_param_gate_clk mpmu_gate_clks[] = {
	{MMP2_CLK_I2S0, "i2s0_clk", "i2s0_pll", CLK_SET_RATE_PARENT, MPMU_ACGR, 0x200000, 0x200000, 0x0, 0, &acgr_lock},
	{MMP2_CLK_I2S1, "i2s1_clk", "i2s1_pll", CLK_SET_RATE_PARENT, MPMU_ACGR, 0x100000, 0x100000, 0x0, 0, &acgr_lock},
};

Annotation

Implementation Notes