drivers/clk/mmp/clk-of-pxa168.c

Source file repositories/reference/linux-study-clean/drivers/clk/mmp/clk-of-pxa168.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/mmp/clk-of-pxa168.c
Extension
.c
Size
14287 bytes
Lines
341
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct pxa168_clk_unit {
	struct mmp_clk_unit unit;
	void __iomem *mpmu_base;
	void __iomem *apmu_base;
	void __iomem *apbc_base;
};

static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
	{PXA168_CLK_CLK32, "clk32", NULL, 0, 32768},
	{PXA168_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000},
	{PXA168_CLK_PLL1, "pll1", NULL, 0, 624000000},
	{PXA168_CLK_USB_PLL, "usb_pll", NULL, 0, 480000000},
};

static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
	{PXA168_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
	{PXA168_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
	{PXA168_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
	{PXA168_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
	{PXA168_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
	{PXA168_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
	{PXA168_CLK_PLL1_24, "pll1_24", "pll1_12", 1, 2, 0},
	{PXA168_CLK_PLL1_48, "pll1_48", "pll1_24", 1, 2, 0},
	{PXA168_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0},
	{PXA168_CLK_PLL1_192, "pll1_192", "pll1_96", 1, 2, 0},
	{PXA168_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0},
	{PXA168_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 1, 5, 0},
	{PXA168_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 1, 5, 0},
	{PXA168_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
	{PXA168_CLK_PLL1_2_1_10, "pll1_2_1_10", "pll1_2", 1, 10, 0},
	{PXA168_CLK_PLL1_2_3_16, "pll1_2_3_16", "pll1_2", 3, 16, 0},
	{PXA168_CLK_CLK32_2, "clk32_2", "clk32", 1, 2, 0},
};

static struct mmp_clk_factor_masks uart_factor_masks = {
	.factor = 2,
	.num_mask = 0x1fff,
	.den_mask = 0x1fff,
	.num_shift = 16,
	.den_shift = 0,
};

static struct u32_fract uart_factor_tbl[] = {
	{ .numerator = 8125, .denominator = 1536 },	/* 14.745MHZ */
};

static void pxa168_pll_init(struct pxa168_clk_unit *pxa_unit)
{
	struct clk *clk;
	struct mmp_clk_unit *unit = &pxa_unit->unit;

	mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
					ARRAY_SIZE(fixed_rate_clks));

	mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
					ARRAY_SIZE(fixed_factor_clks));

	clk = mmp_clk_register_factor("uart_pll", "pll1_4",
				CLK_SET_RATE_PARENT,
				pxa_unit->mpmu_base + MPMU_UART_PLL,
				&uart_factor_masks, uart_factor_tbl,
				ARRAY_SIZE(uart_factor_tbl), NULL);
	mmp_clk_add(unit, PXA168_CLK_UART_PLL, clk);
}

static DEFINE_SPINLOCK(twsi0_lock);
static DEFINE_SPINLOCK(twsi1_lock);
static const char * const twsi_parent_names[] = {"pll1_2_1_10", "pll1_2_1_5"};

static DEFINE_SPINLOCK(kpc_lock);
static const char * const kpc_parent_names[] = {"clk32", "clk32_2", "pll1_24"};

static DEFINE_SPINLOCK(pwm0_lock);
static DEFINE_SPINLOCK(pwm1_lock);
static DEFINE_SPINLOCK(pwm2_lock);
static DEFINE_SPINLOCK(pwm3_lock);
static const char * const pwm_parent_names[] = {"pll1_48", "clk32"};

static DEFINE_SPINLOCK(uart0_lock);
static DEFINE_SPINLOCK(uart1_lock);
static DEFINE_SPINLOCK(uart2_lock);
static const char * const uart_parent_names[] = {"pll1_2_3_16", "uart_pll"};

static DEFINE_SPINLOCK(ssp0_lock);
static DEFINE_SPINLOCK(ssp1_lock);
static DEFINE_SPINLOCK(ssp2_lock);
static DEFINE_SPINLOCK(ssp3_lock);
static DEFINE_SPINLOCK(ssp4_lock);
static const char * const ssp_parent_names[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};

Annotation

Implementation Notes