drivers/clk/mvebu/ap-cpu-clk.c

Source file repositories/reference/linux-study-clean/drivers/clk/mvebu/ap-cpu-clk.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/mvebu/ap-cpu-clk.c
Extension
.c
Size
11542 bytes
Lines
366
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct cpu_dfs_regs {
	unsigned int divider_reg;
	unsigned int force_reg;
	unsigned int ratio_reg;
	unsigned int ratio_state_reg;
	unsigned int divider_mask;
	unsigned int cluster_offset;
	unsigned int force_mask;
	int divider_offset;
	int divider_ratio;
	int ratio_offset;
	int ratio_state_offset;
	int ratio_state_cluster_offset;
};

/* AP806 CPU DFS register mapping*/
#define AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET		0x278
#define AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET		0x280
#define AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET		0x284
#define AP806_CA72MP2_0_PLL_SR_REG_OFFSET		0xC94

#define AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET		0x14
#define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET		0
#define AP806_PLL_CR_CPU_CLK_DIV_RATIO			0
#define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK \
			(0x3f << AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET)
#define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET	24
#define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK \
			(0x1 << AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET)
#define AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET	16
#define AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET	0
#define AP806_CA72MP2_0_PLL_RATIO_STATE			11

#define STATUS_POLL_PERIOD_US		1
#define STATUS_POLL_TIMEOUT_US		1000000

#define to_ap_cpu_clk(_hw) container_of(_hw, struct ap_cpu_clk, hw)

static const struct cpu_dfs_regs ap806_dfs_regs = {
	.divider_reg = AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET,
	.force_reg = AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET,
	.ratio_reg = AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET,
	.ratio_state_reg = AP806_CA72MP2_0_PLL_SR_REG_OFFSET,
	.divider_mask = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK,
	.cluster_offset = AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET,
	.force_mask = AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK,
	.divider_offset = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET,
	.divider_ratio = AP806_PLL_CR_CPU_CLK_DIV_RATIO,
	.ratio_offset = AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET,
	.ratio_state_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET,
	.ratio_state_cluster_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET,
};

/* AP807 CPU DFS register mapping */
#define AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET		0x278
#define AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET		0x27c
#define AP807_DEVICE_GENERAL_STATUS_6_REG_OFFSET		0xc98
#define AP807_CA72MP2_0_PLL_CR_CLUSTER_OFFSET			0x8
#define AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET			18
#define AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK \
		(0x3f << AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET)
#define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET			12
#define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK \
		(0x3f << AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET)
#define AP807_PLL_CR_CPU_CLK_DIV_RATIO				3
#define AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET		0
#define AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK \
		(0x3 << AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET)
#define AP807_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET		6
#define	AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_OFFSET		20
#define AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_CLUSTER_OFFSET	3

static const struct cpu_dfs_regs ap807_dfs_regs = {
	.divider_reg = AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET,
	.force_reg = AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET,
	.ratio_reg = AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET,
	.ratio_state_reg = AP807_DEVICE_GENERAL_STATUS_6_REG_OFFSET,
	.divider_mask = AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK,
	.cluster_offset = AP807_CA72MP2_0_PLL_CR_CLUSTER_OFFSET,
	.force_mask = AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK,
	.divider_offset = AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET,
	.divider_ratio = AP807_PLL_CR_CPU_CLK_DIV_RATIO,
	.ratio_offset = AP807_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET,
	.ratio_state_offset = AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_OFFSET,
	.ratio_state_cluster_offset =
		AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_CLUSTER_OFFSET
};

/*
 * struct ap806_clk: CPU cluster clock controller instance

Annotation

Implementation Notes