drivers/clk/mvebu/armada-38x.c

Source file repositories/reference/linux-study-clean/drivers/clk/mvebu/armada-38x.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/mvebu/armada-38x.c
Extension
.c
Size
4451 bytes
Lines
167
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Marvell Armada 380/385 SoC clocks
 *
 * Copyright (C) 2014 Marvell
 *
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 * Andrew Lunn <andrew@lunn.ch>
 *
 */

#include <linux/kernel.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include "common.h"

/*
 * SAR[14:10] : Ratios between PCLK0, NBCLK, HCLK and DRAM clocks
 *
 * SAR[15]    : TCLK frequency
 *		 0 = 250 MHz
 *		 1 = 200 MHz
 */

#define SAR_A380_TCLK_FREQ_OPT		  15
#define SAR_A380_TCLK_FREQ_OPT_MASK	  0x1
#define SAR_A380_CPU_DDR_L2_FREQ_OPT	  10
#define SAR_A380_CPU_DDR_L2_FREQ_OPT_MASK 0x1F

static const u32 armada_38x_tclk_frequencies[] __initconst = {
	250000000,
	200000000,
};

static u32 __init armada_38x_get_tclk_freq(void __iomem *sar)
{
	u8 tclk_freq_select;

	tclk_freq_select = ((readl(sar) >> SAR_A380_TCLK_FREQ_OPT) &
			    SAR_A380_TCLK_FREQ_OPT_MASK);
	return armada_38x_tclk_frequencies[tclk_freq_select];
}

static const u32 armada_38x_cpu_frequencies[] __initconst = {
	666 * 1000 * 1000,  0, 800 * 1000 * 1000, 0,
	1066 * 1000 * 1000, 0, 1200 * 1000 * 1000, 0,
	1332 * 1000 * 1000, 0, 0, 0,
	1600 * 1000 * 1000, 0, 0, 0,
	1866 * 1000 * 1000, 0, 0, 2000 * 1000 * 1000,
};

static u32 __init armada_38x_get_cpu_freq(void __iomem *sar)
{
	u8 cpu_freq_select;

	cpu_freq_select = ((readl(sar) >> SAR_A380_CPU_DDR_L2_FREQ_OPT) &
			   SAR_A380_CPU_DDR_L2_FREQ_OPT_MASK);
	if (cpu_freq_select >= ARRAY_SIZE(armada_38x_cpu_frequencies)) {
		pr_err("Selected CPU frequency (%d) unsupported\n",
			cpu_freq_select);
		return 0;
	}

	return armada_38x_cpu_frequencies[cpu_freq_select];
}

enum { A380_CPU_TO_DDR, A380_CPU_TO_L2 };

static const struct coreclk_ratio armada_38x_coreclk_ratios[] __initconst = {
	{ .id = A380_CPU_TO_L2,	 .name = "l2clk" },
	{ .id = A380_CPU_TO_DDR, .name = "ddrclk" },
};

static const int armada_38x_cpu_l2_ratios[32][2] __initconst = {
	{1, 2}, {0, 1}, {1, 2}, {0, 1},
	{1, 2}, {0, 1}, {1, 2}, {0, 1},
	{1, 2}, {0, 1}, {0, 1}, {0, 1},
	{1, 2}, {0, 1}, {0, 1}, {0, 1},
	{1, 2}, {0, 1}, {0, 1}, {1, 2},
	{0, 1}, {0, 1}, {0, 1}, {0, 1},
	{0, 1}, {0, 1}, {0, 1}, {0, 1},
	{0, 1}, {0, 1}, {0, 1}, {0, 1},
};

static const int armada_38x_cpu_ddr_ratios[32][2] __initconst = {
	{0, 1}, {0, 1}, {0, 1}, {0, 1},
	{1, 2}, {0, 1}, {0, 1}, {0, 1},
	{1, 2}, {0, 1}, {0, 1}, {0, 1},

Annotation

Implementation Notes