drivers/clk/mvebu/orion.c

Source file repositories/reference/linux-study-clean/drivers/clk/mvebu/orion.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/mvebu/orion.c
Extension
.c
Size
6251 bytes
Lines
279
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Marvell Orion SoC clocks
 *
 * Copyright (C) 2014 Thomas Petazzoni
 *
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 */

#include <linux/kernel.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include "common.h"

static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = {
	{ .id = 0, .name = "ddrclk", }
};

/*
 * Orion 5181
 */

#define SAR_MV88F5181_TCLK_FREQ      8
#define SAR_MV88F5181_TCLK_FREQ_MASK 0x3

static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar)
{
	u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) &
		SAR_MV88F5181_TCLK_FREQ_MASK;
	if (opt == 0)
		return 133333333;
	else if (opt == 1)
		return 150000000;
	else if (opt == 2)
		return 166666667;
	else
		return 0;
}

#define SAR_MV88F5181_CPU_FREQ       4
#define SAR_MV88F5181_CPU_FREQ_MASK  0xf

static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar)
{
	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
		SAR_MV88F5181_CPU_FREQ_MASK;
	if (opt == 0)
		return 333333333;
	else if (opt == 1 || opt == 2)
		return 400000000;
	else if (opt == 3)
		return 500000000;
	else
		return 0;
}

static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id,
					   int *mult, int *div)
{
	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
		SAR_MV88F5181_CPU_FREQ_MASK;
	if (opt == 0 || opt == 1) {
		*mult = 1;
		*div  = 2;
	} else if (opt == 2 || opt == 3) {
		*mult = 1;
		*div  = 3;
	} else {
		*mult = 0;
		*div  = 1;
	}
}

static const struct coreclk_soc_desc mv88f5181_coreclks = {
	.get_tclk_freq = mv88f5181_get_tclk_freq,
	.get_cpu_freq = mv88f5181_get_cpu_freq,
	.get_clk_ratio = mv88f5181_get_clk_ratio,
	.ratios = orion_coreclk_ratios,
	.num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
};

static void __init mv88f5181_clk_init(struct device_node *np)
{
	return mvebu_coreclk_setup(np, &mv88f5181_coreclks);
}

CLK_OF_DECLARE(mv88f5181_clk, "marvell,mv88f5181-core-clock", mv88f5181_clk_init);

Annotation

Implementation Notes