drivers/clk/nuvoton/clk-ma35d1.c

Source file repositories/reference/linux-study-clean/drivers/clk/nuvoton/clk-ma35d1.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/nuvoton/clk-ma35d1.c
Extension
.c
Size
39453 bytes
Lines
1059
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2023 Nuvoton Technology Corp.
 * Author: Chi-Fang Li <cfli0@nuvoton.com>
 */

#include <linux/clk-provider.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <dt-bindings/clock/nuvoton,ma35d1-clk.h>

#include "clk-ma35d1.h"

static DEFINE_SPINLOCK(ma35d1_lock);

#define PLL_MAX_NUM		5

/* Clock Control Registers Offset */
#define REG_CLK_PWRCTL		0x00
#define REG_CLK_SYSCLK0		0x04
#define REG_CLK_SYSCLK1		0x08
#define REG_CLK_APBCLK0		0x0c
#define REG_CLK_APBCLK1		0x10
#define REG_CLK_APBCLK2		0x14
#define REG_CLK_CLKSEL0		0x18
#define REG_CLK_CLKSEL1		0x1c
#define REG_CLK_CLKSEL2		0x20
#define REG_CLK_CLKSEL3		0x24
#define REG_CLK_CLKSEL4		0x28
#define REG_CLK_CLKDIV0		0x2c
#define REG_CLK_CLKDIV1		0x30
#define REG_CLK_CLKDIV2		0x34
#define REG_CLK_CLKDIV3		0x38
#define REG_CLK_CLKDIV4		0x3c
#define REG_CLK_CLKOCTL		0x40
#define REG_CLK_STATUS		0x50
#define REG_CLK_PLL0CTL0	0x60
#define REG_CLK_PLL2CTL0	0x80
#define REG_CLK_PLL2CTL1	0x84
#define REG_CLK_PLL2CTL2	0x88
#define REG_CLK_PLL3CTL0	0x90
#define REG_CLK_PLL3CTL1	0x94
#define REG_CLK_PLL3CTL2	0x98
#define REG_CLK_PLL4CTL0	0xa0
#define REG_CLK_PLL4CTL1	0xa4
#define REG_CLK_PLL4CTL2	0xa8
#define REG_CLK_PLL5CTL0	0xb0
#define REG_CLK_PLL5CTL1	0xb4
#define REG_CLK_PLL5CTL2	0xb8
#define REG_CLK_CLKDCTL		0xc0
#define REG_CLK_CLKDSTS		0xc4
#define REG_CLK_CDUPB		0xc8
#define REG_CLK_CDLOWB		0xcc
#define REG_CLK_CKFLTRCTL	0xd0
#define REG_CLK_TESTCLK		0xf0
#define REG_CLK_PLLCTL		0x40

#define PLL_MODE_INT            0
#define PLL_MODE_FRAC           1
#define PLL_MODE_SS             2

static const struct clk_parent_data ca35clk_sel_clks[] = {
	{ .fw_name = "hxt", },
	{ .fw_name = "capll", },
	{ .fw_name = "ddrpll", },
};

static const struct clk_parent_data sysclk0_sel_clks[] = {
	{ .fw_name = "epll_div2", },
	{ .fw_name = "syspll", },
};

static const struct clk_parent_data sysclk1_sel_clks[] = {
	{ .fw_name = "hxt", },
	{ .fw_name = "syspll", },
};

static const struct clk_parent_data axiclk_sel_clks[] = {
	{ .fw_name = "capll_div2", },
	{ .fw_name = "capll_div4", },
};

static const struct clk_parent_data ccap_sel_clks[] = {
	{ .fw_name = "hxt", },
	{ .fw_name = "vpll", },
	{ .fw_name = "apll", },
	{ .fw_name = "syspll", },

Annotation

Implementation Notes