drivers/clk/nuvoton/clk-ma35d1-divider.c

Source file repositories/reference/linux-study-clean/drivers/clk/nuvoton/clk-ma35d1-divider.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/nuvoton/clk-ma35d1-divider.c
Extension
.c
Size
3398 bytes
Lines
134
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ma35d1_adc_clk_div {
	struct clk_hw hw;
	void __iomem *reg;
	u8 shift;
	u8 width;
	u32 mask;
	const struct clk_div_table *table;
	/* protects concurrent access to clock divider registers */
	spinlock_t *lock;
};

static inline struct ma35d1_adc_clk_div *to_ma35d1_adc_clk_div(struct clk_hw *_hw)
{
	return container_of(_hw, struct ma35d1_adc_clk_div, hw);
}

static unsigned long ma35d1_clkdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
	unsigned int val;
	struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw);

	val = readl_relaxed(dclk->reg) >> dclk->shift;
	val &= clk_div_mask(dclk->width);
	val += 1;
	return divider_recalc_rate(hw, parent_rate, val, dclk->table,
				   CLK_DIVIDER_ROUND_CLOSEST, dclk->width);
}

static int ma35d1_clkdiv_determine_rate(struct clk_hw *hw,
					struct clk_rate_request *req)
{
	struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw);

	return divider_determine_rate(hw, req, dclk->table, dclk->width,
				      CLK_DIVIDER_ROUND_CLOSEST);
}

static int ma35d1_clkdiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate)
{
	int value;
	unsigned long flags = 0;
	u32 data;
	struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw);

	value = divider_get_val(rate, parent_rate, dclk->table,
				dclk->width, CLK_DIVIDER_ROUND_CLOSEST);

	spin_lock_irqsave(dclk->lock, flags);

	data = readl_relaxed(dclk->reg);
	data &= ~(clk_div_mask(dclk->width) << dclk->shift);
	data |= (value - 1) << dclk->shift;
	data |= dclk->mask;
	writel_relaxed(data, dclk->reg);

	spin_unlock_irqrestore(dclk->lock, flags);
	return 0;
}

static const struct clk_ops ma35d1_adc_clkdiv_ops = {
	.recalc_rate = ma35d1_clkdiv_recalc_rate,
	.determine_rate = ma35d1_clkdiv_determine_rate,
	.set_rate = ma35d1_clkdiv_set_rate,
};

struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name,
				     struct clk_hw *parent_hw, spinlock_t *lock,
				     unsigned long flags, void __iomem *reg,
				     u8 shift, u8 width, u32 mask_bit)
{
	struct ma35d1_adc_clk_div *div;
	struct clk_init_data init;
	struct clk_div_table *table;
	struct clk_parent_data pdata = { .index = 0 };
	u32 max_div, min_div;
	struct clk_hw *hw;
	int ret;
	int i;

	div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
	if (!div)
		return ERR_PTR(-ENOMEM);

	max_div = clk_div_mask(width) + 1;
	min_div = 1;

	table = devm_kcalloc(dev, max_div + 1, sizeof(*table), GFP_KERNEL);
	if (!table)
		return ERR_PTR(-ENOMEM);

Annotation

Implementation Notes