drivers/clk/nxp/clk-lpc18xx-cgu.c

Source file repositories/reference/linux-study-clean/drivers/clk/nxp/clk-lpc18xx-cgu.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/nxp/clk-lpc18xx-cgu.c
Extension
.c
Size
18918 bytes
Lines
669
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct lpc18xx_cgu_src_clk_div {
	u8 clk_id;
	u8 n_parents;
	struct clk_divider	div;
	struct clk_mux		mux;
	struct clk_gate		gate;
};

#define LPC1XX_CGU_SRC_CLK_DIV(_id, _width, _table)	\
{							\
	.clk_id = CLK_SRC_ ##_id,			\
	.n_parents = ARRAY_SIZE(lpc18xx_cgu_ ##_table),	\
	.div = {					\
		.shift = 2,				\
		.width = _width,			\
	},						\
	.mux = {					\
		.mask = 0x1f,				\
		.shift = 24,				\
		.table = lpc18xx_cgu_ ##_table,		\
	},						\
	.gate = {					\
		.bit_idx = 0,				\
		.flags = CLK_GATE_SET_TO_DISABLE,	\
	},						\
}

static struct lpc18xx_cgu_src_clk_div lpc18xx_cgu_src_clk_divs[] = {
	LPC1XX_CGU_SRC_CLK_DIV(IDIVA, 2, idiva_src_ids),
	LPC1XX_CGU_SRC_CLK_DIV(IDIVB, 4, idivbcde_src_ids),
	LPC1XX_CGU_SRC_CLK_DIV(IDIVC, 4, idivbcde_src_ids),
	LPC1XX_CGU_SRC_CLK_DIV(IDIVD, 4, idivbcde_src_ids),
	LPC1XX_CGU_SRC_CLK_DIV(IDIVE, 8, idivbcde_src_ids),
};

struct lpc18xx_cgu_base_clk {
	u8 clk_id;
	u8 n_parents;
	struct clk_mux mux;
	struct clk_gate gate;
};

#define LPC1XX_CGU_BASE_CLK(_id, _table, _flags)	\
{							\
	.clk_id = BASE_ ##_id ##_CLK,			\
	.n_parents = ARRAY_SIZE(lpc18xx_cgu_ ##_table),	\
	.mux = {					\
		.mask = 0x1f,				\
		.shift = 24,				\
		.table = lpc18xx_cgu_ ##_table,		\
		.flags = _flags,			\
	},						\
	.gate = {					\
		.bit_idx = 0,				\
		.flags = CLK_GATE_SET_TO_DISABLE,	\
	},						\
}

static struct lpc18xx_cgu_base_clk lpc18xx_cgu_base_clks[] = {
	LPC1XX_CGU_BASE_CLK(SAFE,	base_irc_src_ids, CLK_MUX_READ_ONLY),
	LPC1XX_CGU_BASE_CLK(USB0,	base_usb0_src_ids,   0),
	LPC1XX_CGU_BASE_CLK(PERIPH,	base_common_src_ids, 0),
	LPC1XX_CGU_BASE_CLK(USB1,	base_all_src_ids,    0),
	LPC1XX_CGU_BASE_CLK(CPU,	base_common_src_ids, 0),
	LPC1XX_CGU_BASE_CLK(SPIFI,	base_common_src_ids, 0),
	LPC1XX_CGU_BASE_CLK(SPI,	base_common_src_ids, 0),
	LPC1XX_CGU_BASE_CLK(PHY_RX,	base_common_src_ids, 0),
	LPC1XX_CGU_BASE_CLK(PHY_TX,	base_common_src_ids, 0),
	LPC1XX_CGU_BASE_CLK(APB1,	base_common_src_ids, 0),
	LPC1XX_CGU_BASE_CLK(APB3,	base_common_src_ids, 0),
	LPC1XX_CGU_BASE_CLK(LCD,	base_common_src_ids, 0),
	LPC1XX_CGU_BASE_CLK(ADCHS,	base_common_src_ids, 0),
	LPC1XX_CGU_BASE_CLK(SDIO,	base_common_src_ids, 0),
	LPC1XX_CGU_BASE_CLK(SSP0,	base_common_src_ids, 0),
	LPC1XX_CGU_BASE_CLK(SSP1,	base_common_src_ids, 0),
	LPC1XX_CGU_BASE_CLK(UART0,	base_common_src_ids, 0),
	LPC1XX_CGU_BASE_CLK(UART1,	base_common_src_ids, 0),
	LPC1XX_CGU_BASE_CLK(UART2,	base_common_src_ids, 0),
	LPC1XX_CGU_BASE_CLK(UART3,	base_common_src_ids, 0),
	LPC1XX_CGU_BASE_CLK(OUT,	base_all_src_ids,    0),
	{ /* 21 reserved */ },
	{ /* 22 reserved */ },
	{ /* 23 reserved */ },
	{ /* 24 reserved */ },
	LPC1XX_CGU_BASE_CLK(AUDIO,	base_common_src_ids, 0),
	LPC1XX_CGU_BASE_CLK(CGU_OUT0,	base_all_src_ids,    0),
	LPC1XX_CGU_BASE_CLK(CGU_OUT1,	base_all_src_ids,    0),
};

struct lpc18xx_pll {

Annotation

Implementation Notes