drivers/clk/pistachio/clk-pistachio.c

Source file repositories/reference/linux-study-clean/drivers/clk/pistachio/clk-pistachio.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/pistachio/clk-pistachio.c
Extension
.c
Size
14229 bytes
Lines
336
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Pistachio SoC clock controllers
 *
 * Copyright (C) 2014 Google, Inc.
 */

#include <linux/clk-provider.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of.h>

#include <dt-bindings/clock/pistachio-clk.h>

#include "clk.h"

static struct pistachio_gate pistachio_gates[] __initdata = {
	GATE(CLK_MIPS, "mips", "mips_div", 0x104, 0),
	GATE(CLK_AUDIO_IN, "audio_in", "audio_clk_in_gate", 0x104, 1),
	GATE(CLK_AUDIO, "audio", "audio_div", 0x104, 2),
	GATE(CLK_I2S, "i2s", "i2s_div", 0x104, 3),
	GATE(CLK_SPDIF, "spdif", "spdif_div", 0x104, 4),
	GATE(CLK_AUDIO_DAC, "audio_dac", "audio_dac_div", 0x104, 5),
	GATE(CLK_RPU_V, "rpu_v", "rpu_v_div", 0x104, 6),
	GATE(CLK_RPU_L, "rpu_l", "rpu_l_div", 0x104, 7),
	GATE(CLK_RPU_SLEEP, "rpu_sleep", "rpu_sleep_div", 0x104, 8),
	GATE(CLK_WIFI_PLL_GATE, "wifi_pll_gate", "wifi_pll_mux", 0x104, 9),
	GATE(CLK_RPU_CORE, "rpu_core", "rpu_core_div", 0x104, 10),
	GATE(CLK_WIFI_ADC, "wifi_adc", "wifi_div8_mux", 0x104, 11),
	GATE(CLK_WIFI_DAC, "wifi_dac", "wifi_div4_mux", 0x104, 12),
	GATE(CLK_USB_PHY, "usb_phy", "usb_phy_div", 0x104, 13),
	GATE(CLK_ENET_IN, "enet_in", "enet_clk_in_gate", 0x104, 14),
	GATE(CLK_ENET, "enet", "enet_div", 0x104, 15),
	GATE(CLK_UART0, "uart0", "uart0_div", 0x104, 16),
	GATE(CLK_UART1, "uart1", "uart1_div", 0x104, 17),
	GATE(CLK_PERIPH_SYS, "periph_sys", "sys_internal_div", 0x104, 18),
	GATE(CLK_SPI0, "spi0", "spi0_div", 0x104, 19),
	GATE(CLK_SPI1, "spi1", "spi1_div", 0x104, 20),
	GATE(CLK_EVENT_TIMER, "event_timer", "event_timer_div", 0x104, 21),
	GATE(CLK_AUX_ADC_INTERNAL, "aux_adc_internal", "sys_internal_div",
	     0x104, 22),
	GATE(CLK_AUX_ADC, "aux_adc", "aux_adc_div", 0x104, 23),
	GATE(CLK_SD_HOST, "sd_host", "sd_host_div", 0x104, 24),
	GATE(CLK_BT, "bt", "bt_div", 0x104, 25),
	GATE(CLK_BT_DIV4, "bt_div4", "bt_div4_div", 0x104, 26),
	GATE(CLK_BT_DIV8, "bt_div8", "bt_div8_div", 0x104, 27),
	GATE(CLK_BT_1MHZ, "bt_1mhz", "bt_1mhz_div", 0x104, 28),
};

static struct pistachio_fixed_factor pistachio_ffs[] __initdata = {
	FIXED_FACTOR(CLK_WIFI_DIV4, "wifi_div4", "wifi_pll", 4),
	FIXED_FACTOR(CLK_WIFI_DIV8, "wifi_div8", "wifi_pll", 8),
};

static struct pistachio_div pistachio_divs[] __initdata = {
	DIV(CLK_MIPS_INTERNAL_DIV, "mips_internal_div", "mips_pll_mux",
	    0x204, 2),
	DIV(CLK_MIPS_DIV, "mips_div", "mips_internal_div", 0x208, 8),
	DIV_F(CLK_AUDIO_DIV, "audio_div", "audio_mux",
		0x20c, 8, CLK_DIVIDER_ROUND_CLOSEST),
	DIV_F(CLK_I2S_DIV, "i2s_div", "audio_pll_mux",
		0x210, 8, CLK_DIVIDER_ROUND_CLOSEST),
	DIV_F(CLK_SPDIF_DIV, "spdif_div", "audio_pll_mux",
		0x214, 8, CLK_DIVIDER_ROUND_CLOSEST),
	DIV_F(CLK_AUDIO_DAC_DIV, "audio_dac_div", "audio_pll_mux",
		0x218, 8, CLK_DIVIDER_ROUND_CLOSEST),
	DIV(CLK_RPU_V_DIV, "rpu_v_div", "rpu_v_pll_mux", 0x21c, 2),
	DIV(CLK_RPU_L_DIV, "rpu_l_div", "rpu_l_mux", 0x220, 2),
	DIV(CLK_RPU_SLEEP_DIV, "rpu_sleep_div", "xtal", 0x224, 10),
	DIV(CLK_RPU_CORE_DIV, "rpu_core_div", "rpu_core_mux", 0x228, 3),
	DIV(CLK_USB_PHY_DIV, "usb_phy_div", "sys_internal_div", 0x22c, 6),
	DIV(CLK_ENET_DIV, "enet_div", "enet_mux", 0x230, 6),
	DIV_F(CLK_UART0_INTERNAL_DIV, "uart0_internal_div", "sys_pll_mux",
	      0x234, 3, CLK_DIVIDER_ROUND_CLOSEST),
	DIV_F(CLK_UART0_DIV, "uart0_div", "uart0_internal_div", 0x238, 10,
	      CLK_DIVIDER_ROUND_CLOSEST),
	DIV_F(CLK_UART1_INTERNAL_DIV, "uart1_internal_div", "sys_pll_mux",
	      0x23c, 3, CLK_DIVIDER_ROUND_CLOSEST),
	DIV_F(CLK_UART1_DIV, "uart1_div", "uart1_internal_div", 0x240, 10,
	      CLK_DIVIDER_ROUND_CLOSEST),
	DIV(CLK_SYS_INTERNAL_DIV, "sys_internal_div", "sys_pll_mux", 0x244, 3),
	DIV(CLK_SPI0_INTERNAL_DIV, "spi0_internal_div", "sys_pll_mux",
	    0x248, 3),
	DIV(CLK_SPI0_DIV, "spi0_div", "spi0_internal_div", 0x24c, 7),
	DIV(CLK_SPI1_INTERNAL_DIV, "spi1_internal_div", "sys_pll_mux",
	    0x250, 3),
	DIV(CLK_SPI1_DIV, "spi1_div", "spi1_internal_div", 0x254, 7),
	DIV(CLK_EVENT_TIMER_INTERNAL_DIV, "event_timer_internal_div",
	    "event_timer_mux", 0x258, 3),

Annotation

Implementation Notes