drivers/clk/pxa/clk-pxa3xx.c
Source file repositories/reference/linux-study-clean/drivers/clk/pxa/clk-pxa3xx.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/clk/pxa/clk-pxa3xx.c- Extension
.c- Size
- 15827 bytes
- Lines
- 464
- Domain
- Driver Families
- Bucket
- drivers/clk
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/io.hlinux/clk.hlinux/clk-provider.hlinux/clkdev.hlinux/of.hlinux/soc/pxa/cpu.hlinux/soc/pxa/smemc.hlinux/clk/pxa.hdt-bindings/clock/pxa-clock.hclk-pxa.h
Detected Declarations
struct dummy_clkfunction pxa3xx_get_clk_frequency_khzfunction pxa3xx_clk_update_accrfunction clk_pxa3xx_ac97_get_ratefunction clk_pxa3xx_smemc_get_ratefunction pxa3xx_is_ring_osc_forcedfunction clk_pxa3xx_system_bus_get_ratefunction clk_pxa3xx_system_bus_get_parentfunction clk_pxa3xx_core_get_ratefunction clk_pxa3xx_core_get_parentfunction clk_pxa3xx_run_get_ratefunction clk_pxa3xx_cpll_get_ratefunction pxa3xx_register_corefunction pxa3xx_register_pllsfunction pxa3xx_dummy_clocks_initfunction pxa3xx_base_clocks_initfunction pxa3xx_clocks_initfunction pxa3xx_dt_clocks_init
Annotated Snippet
struct dummy_clk {
const char *con_id;
const char *dev_id;
const char *parent;
};
static struct dummy_clk dummy_clks[] __initdata = {
DUMMY_CLK(NULL, "pxa93x-gpio", "osc_13mhz"),
DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
DUMMY_CLK(NULL, "pxa3xx-pwri2c.1", "osc_13mhz"),
};
static void __init pxa3xx_dummy_clocks_init(void)
{
struct clk *clk;
struct dummy_clk *d;
const char *name;
int i;
for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
d = &dummy_clks[i];
name = d->dev_id ? d->dev_id : d->con_id;
clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
clk_register_clkdev(clk, d->con_id, d->dev_id);
}
}
static void __init pxa3xx_base_clocks_init(void __iomem *oscc_reg)
{
struct clk *clk;
pxa3xx_register_plls();
pxa3xx_register_core();
clk_register_clk_pxa3xx_system_bus();
clk_register_clk_pxa3xx_ac97();
clk_register_clk_pxa3xx_smemc();
clk = clk_register_gate(NULL, "CLK_POUT",
"osc_13mhz", 0, oscc_reg, 11, 0, NULL);
clk_register_clkdev(clk, "CLK_POUT", NULL);
clkdev_pxa_register(CLK_OSTIMER, "OSTIMER0", NULL,
clk_register_fixed_factor(NULL, "os-timer0",
"osc_13mhz", 0, 1, 4));
}
int __init pxa3xx_clocks_init(void __iomem *regs, void __iomem *oscc_reg)
{
int ret;
clk_regs = regs;
pxa3xx_base_clocks_init(oscc_reg);
pxa3xx_dummy_clocks_init();
ret = clk_pxa_cken_init(pxa3xx_clocks, ARRAY_SIZE(pxa3xx_clocks), regs);
if (ret)
return ret;
if (cpu_is_pxa320())
return clk_pxa_cken_init(pxa320_clocks,
ARRAY_SIZE(pxa320_clocks), regs);
if (cpu_is_pxa300() || cpu_is_pxa310())
return clk_pxa_cken_init(pxa300_310_clocks,
ARRAY_SIZE(pxa300_310_clocks), regs);
return clk_pxa_cken_init(pxa93x_clocks, ARRAY_SIZE(pxa93x_clocks), regs);
}
static void __init pxa3xx_dt_clocks_init(struct device_node *np)
{
pxa3xx_clocks_init(ioremap(0x41340000, 0x10), ioremap(0x41350000, 4));
clk_pxa_dt_common_init(np);
}
CLK_OF_DECLARE(pxa_clks, "marvell,pxa300-clocks", pxa3xx_dt_clocks_init);
Annotation
- Immediate include surface: `linux/io.h`, `linux/clk.h`, `linux/clk-provider.h`, `linux/clkdev.h`, `linux/of.h`, `linux/soc/pxa/cpu.h`, `linux/soc/pxa/smemc.h`, `linux/clk/pxa.h`.
- Detected declarations: `struct dummy_clk`, `function pxa3xx_get_clk_frequency_khz`, `function pxa3xx_clk_update_accr`, `function clk_pxa3xx_ac97_get_rate`, `function clk_pxa3xx_smemc_get_rate`, `function pxa3xx_is_ring_osc_forced`, `function clk_pxa3xx_system_bus_get_rate`, `function clk_pxa3xx_system_bus_get_parent`, `function clk_pxa3xx_core_get_rate`, `function clk_pxa3xx_core_get_parent`.
- Atlas domain: Driver Families / drivers/clk.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.