drivers/clk/qcom/apcs-sdx55.c
Source file repositories/reference/linux-study-clean/drivers/clk/qcom/apcs-sdx55.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/clk/qcom/apcs-sdx55.c- Extension
.c- Size
- 3908 bytes
- Lines
- 148
- Domain
- Driver Families
- Bucket
- drivers/clk
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/clk.hlinux/clk-provider.hlinux/cpu.hlinux/kernel.hlinux/module.hlinux/platform_device.hlinux/pm_domain.hlinux/regmap.hlinux/slab.hclk-regmap.hclk-regmap-mux-div.h
Detected Declarations
function a7cc_notifier_cbfunction qcom_apcs_sdx55_clk_probefunction qcom_apcs_sdx55_clk_remove
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/*
* Qualcomm SDX55 APCS clock controller driver
*
* Copyright (c) 2020, Linaro Limited
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/cpu.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include "clk-regmap.h"
#include "clk-regmap-mux-div.h"
static const u32 apcs_mux_clk_parent_map[] = { 0, 1, 5 };
static const struct clk_parent_data pdata[] = {
{ .fw_name = "ref" },
{ .fw_name = "aux" },
{ .fw_name = "pll" },
};
/*
* We use the notifier function for switching to a temporary safe configuration
* (mux and divider), while the A7 PLL is reconfigured.
*/
static int a7cc_notifier_cb(struct notifier_block *nb, unsigned long event,
void *data)
{
int ret = 0;
struct clk_regmap_mux_div *md = container_of(nb,
struct clk_regmap_mux_div,
clk_nb);
if (event == PRE_RATE_CHANGE)
/* set the mux and divider to safe frequency (400mhz) */
ret = mux_div_set_src_div(md, 1, 2);
return notifier_from_errno(ret);
}
static int qcom_apcs_sdx55_clk_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device *parent = dev->parent;
struct device *cpu_dev;
struct clk_regmap_mux_div *a7cc;
struct regmap *regmap;
struct clk_init_data init = { };
int ret;
regmap = dev_get_regmap(parent, NULL);
if (!regmap) {
dev_err(dev, "Failed to get parent regmap\n");
return -ENODEV;
}
a7cc = devm_kzalloc(dev, sizeof(*a7cc), GFP_KERNEL);
if (!a7cc)
return -ENOMEM;
init.name = "a7mux";
init.parent_data = pdata;
init.num_parents = ARRAY_SIZE(pdata);
init.ops = &clk_regmap_mux_div_ops;
a7cc->clkr.hw.init = &init;
a7cc->clkr.regmap = regmap;
a7cc->reg_offset = 0x8;
a7cc->hid_width = 5;
a7cc->hid_shift = 0;
a7cc->src_width = 3;
a7cc->src_shift = 8;
a7cc->parent_map = apcs_mux_clk_parent_map;
a7cc->pclk = devm_clk_get(parent, "pll");
if (IS_ERR(a7cc->pclk))
return dev_err_probe(dev, PTR_ERR(a7cc->pclk),
"Failed to get PLL clk\n");
a7cc->clk_nb.notifier_call = a7cc_notifier_cb;
ret = clk_notifier_register(a7cc->pclk, &a7cc->clk_nb);
if (ret)
return dev_err_probe(dev, ret,
Annotation
- Immediate include surface: `linux/clk.h`, `linux/clk-provider.h`, `linux/cpu.h`, `linux/kernel.h`, `linux/module.h`, `linux/platform_device.h`, `linux/pm_domain.h`, `linux/regmap.h`.
- Detected declarations: `function a7cc_notifier_cb`, `function qcom_apcs_sdx55_clk_probe`, `function qcom_apcs_sdx55_clk_remove`.
- Atlas domain: Driver Families / drivers/clk.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.