drivers/clk/qcom/apss-ipq5424.c

Source file repositories/reference/linux-study-clean/drivers/clk/qcom/apss-ipq5424.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/qcom/apss-ipq5424.c
Extension
.c
Size
6382 bytes
Lines
259
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
 * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/interconnect-provider.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>

#include <dt-bindings/arm/qcom,ids.h>
#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/interconnect/qcom,ipq5424.h>

#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "common.h"

enum {
	DT_XO,
	DT_CLK_REF,
};

enum {
	P_XO,
	P_GPLL0,
	P_APSS_PLL_EARLY,
	P_L3_PLL,
};

static const struct alpha_pll_config apss_pll_config = {
	.l = 0x3b,
	.config_ctl_val = 0x08200920,
	.config_ctl_hi_val = 0x05008001,
	.config_ctl_hi1_val = 0x04000000,
	.user_ctl_val = 0xf,
};

static struct clk_alpha_pll ipq5424_apss_pll = {
	.offset = 0x0,
	.config = &apss_pll_config,
	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290],
	.flags = SUPPORTS_DYNAMIC_UPDATE,
	.clkr = {
		.enable_reg = 0x0,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
			.name = "apss_pll",
			.parent_data = &(const struct clk_parent_data) {
				.index = DT_XO,
			},
			.num_parents = 1,
			.ops = &clk_alpha_pll_huayra_ops,
		},
	},
};

static const struct clk_parent_data parents_apss_silver_clk_src[] = {
	{ .index = DT_XO },
	{ .index = DT_CLK_REF },
	{ .hw = &ipq5424_apss_pll.clkr.hw },
};

static const struct parent_map parents_apss_silver_clk_src_map[] = {
	{ P_XO, 0 },
	{ P_GPLL0, 4 },
	{ P_APSS_PLL_EARLY, 5 },
};

static const struct freq_tbl ftbl_apss_clk_src[] = {
	F(816000000, P_APSS_PLL_EARLY, 1, 0, 0),
	F(1416000000, P_APSS_PLL_EARLY, 1, 0, 0),
	F(1800000000, P_APSS_PLL_EARLY, 1, 0, 0),
	{ }
};

static struct clk_rcg2 apss_silver_clk_src = {
	.cmd_rcgr = 0x0080,
	.freq_tbl = ftbl_apss_clk_src,
	.hid_width = 5,
	.parent_map = parents_apss_silver_clk_src_map,
	.clkr.hw.init = &(struct clk_init_data) {
		.name = "apss_silver_clk_src",

Annotation

Implementation Notes