drivers/clk/qcom/clk-rcg.c
Source file repositories/reference/linux-study-clean/drivers/clk/qcom/clk-rcg.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/clk/qcom/clk-rcg.c- Extension
.c- Size
- 21660 bytes
- Lines
- 914
- Domain
- Driver Families
- Bucket
- drivers/clk
- Inferred role
- Driver Families: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/bitops.hlinux/err.hlinux/export.hlinux/clk-provider.hlinux/regmap.hasm/div64.hclk-rcg.hcommon.h
Detected Declarations
struct frac_entryfunction Copyrightfunction src_to_nsfunction clk_rcg_get_parentfunction reg_to_bankfunction clk_dyn_rcg_get_parentfunction clk_rcg_set_parentfunction md_to_mfunction ns_to_pre_divfunction pre_div_to_nsfunction mn_to_mdfunction ns_m_to_nfunction reg_to_mnctr_modefunction mn_to_nsfunction mn_to_regfunction configure_bankfunction clk_dyn_rcg_set_parentfunction calc_ratefunction clk_rcg_recalc_ratefunction clk_dyn_rcg_recalc_ratefunction _freq_tbl_determine_ratefunction clk_rcg_determine_ratefunction clk_dyn_rcg_determine_ratefunction clk_rcg_bypass_determine_ratefunction __clk_rcg_set_ratefunction clk_rcg_set_ratefunction clk_rcg_set_floor_ratefunction clk_rcg_bypass_set_ratefunction clk_rcg_bypass2_determine_ratefunction clk_rcg_bypass2_set_ratefunction clk_rcg_bypass2_set_rate_and_parentfunction clk_rcg_pixel_determine_ratefunction clk_rcg_pixel_set_ratefunction clk_rcg_pixel_set_rate_and_parentfunction clk_rcg_esc_determine_ratefunction clk_rcg_esc_set_ratefunction clk_rcg_esc_set_rate_and_parentfunction clk_set_ratefunction clk_rcg_lcc_enablefunction clk_rcg_lcc_disablefunction __clk_dyn_rcg_set_ratefunction clk_dyn_rcg_set_ratefunction clk_dyn_rcg_set_rate_and_parentexport clk_rcg_opsexport clk_rcg_floor_opsexport clk_rcg_bypass_opsexport clk_rcg_bypass2_opsexport clk_rcg_pixel_ops
Annotated Snippet
struct frac_entry {
int num;
int den;
};
static const struct frac_entry pixel_table[] = {
{ 1, 1 },
{ 1, 2 },
{ 1, 3 },
{ 3, 16 },
{ }
};
static int clk_rcg_pixel_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
int delta = 100000;
const struct frac_entry *frac = pixel_table;
unsigned long request, src_rate;
for (; frac->num; frac++) {
request = (req->rate * frac->den) / frac->num;
src_rate = clk_hw_round_rate(req->best_parent_hw, request);
if ((src_rate < (request - delta)) ||
(src_rate > (request + delta)))
continue;
req->best_parent_rate = src_rate;
req->rate = (src_rate * frac->num) / frac->den;
return 0;
}
return -EINVAL;
}
static int clk_rcg_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_rcg *rcg = to_clk_rcg(hw);
int delta = 100000;
const struct frac_entry *frac = pixel_table;
unsigned long request;
struct freq_tbl f = { 0 };
u32 ns, src;
int i, ret, num_parents = clk_hw_get_num_parents(hw);
ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
if (ret)
return ret;
src = ns_to_src(&rcg->s, ns);
for (i = 0; i < num_parents; i++) {
if (src == rcg->s.parent_map[i].cfg) {
f.src = rcg->s.parent_map[i].src;
break;
}
}
/* bypass the pre divider */
f.pre_div = 1;
/* let us find appropriate m/n values for this */
for (; frac->num; frac++) {
request = (rate * frac->den) / frac->num;
if ((parent_rate < (request - delta)) ||
(parent_rate > (request + delta)))
continue;
f.m = frac->num;
f.n = frac->den;
return __clk_rcg_set_rate(rcg, &f);
}
return -EINVAL;
}
static int clk_rcg_pixel_set_rate_and_parent(struct clk_hw *hw,
unsigned long rate, unsigned long parent_rate, u8 index)
{
return clk_rcg_pixel_set_rate(hw, rate, parent_rate);
}
static int clk_rcg_esc_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/bitops.h`, `linux/err.h`, `linux/export.h`, `linux/clk-provider.h`, `linux/regmap.h`, `asm/div64.h`, `clk-rcg.h`.
- Detected declarations: `struct frac_entry`, `function Copyright`, `function src_to_ns`, `function clk_rcg_get_parent`, `function reg_to_bank`, `function clk_dyn_rcg_get_parent`, `function clk_rcg_set_parent`, `function md_to_m`, `function ns_to_pre_div`, `function pre_div_to_ns`.
- Atlas domain: Driver Families / drivers/clk.
- Implementation status: integration implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.