drivers/clk/qcom/dispcc-sm8250.c

Source file repositories/reference/linux-study-clean/drivers/clk/qcom/dispcc-sm8250.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/qcom/dispcc-sm8250.c
Extension
.c
Size
39427 bytes
Lines
1396
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {
		disp_cc_pll0_config.config_ctl_hi_val = 0x00002267;
		disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024;
		disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0;
		disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops;
		disp_cc_pll1_config.config_ctl_hi_val = 0x00002267;
		disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;
		disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;
		disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;

		disp_cc_mdss_dp_link_intf_clk.clkr.hw.init->parent_hws[0] =
			&disp_cc_mdss_dp_link_clk_src.clkr.hw;
		disp_cc_mdss_dp_link1_intf_clk.clkr.hw.init->parent_hws[0] =
			&disp_cc_mdss_dp_link1_clk_src.clkr.hw;
		disp_cc_mdss_edp_link_intf_clk.clkr.hw.init->parent_hws[0] =
			&disp_cc_mdss_edp_link_clk_src.clkr.hw;

		disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = NULL;
		disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = NULL;
		disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = NULL;
	} else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {
		static struct clk_rcg2 * const rcgs[] = {
			&disp_cc_mdss_byte0_clk_src,
			&disp_cc_mdss_byte1_clk_src,
			&disp_cc_mdss_dp_aux1_clk_src,
			&disp_cc_mdss_dp_aux_clk_src,
			&disp_cc_mdss_dp_link1_clk_src,
			&disp_cc_mdss_dp_link_clk_src,
			&disp_cc_mdss_dp_pixel1_clk_src,
			&disp_cc_mdss_dp_pixel2_clk_src,
			&disp_cc_mdss_dp_pixel_clk_src,
			&disp_cc_mdss_edp_aux_clk_src,
			&disp_cc_mdss_edp_link_clk_src,
			&disp_cc_mdss_edp_pixel_clk_src,
			&disp_cc_mdss_esc0_clk_src,
			&disp_cc_mdss_esc1_clk_src,
			&disp_cc_mdss_mdp_clk_src,
			&disp_cc_mdss_pclk0_clk_src,
			&disp_cc_mdss_pclk1_clk_src,
			&disp_cc_mdss_rot_clk_src,
			&disp_cc_mdss_vsync_clk_src,
		};
		static struct clk_regmap_div * const divs[] = {
			&disp_cc_mdss_byte0_div_clk_src,
			&disp_cc_mdss_byte1_div_clk_src,
			&disp_cc_mdss_dp_link1_div_clk_src,
			&disp_cc_mdss_dp_link_div_clk_src,
			&disp_cc_mdss_edp_link_div_clk_src,
		};
		unsigned int i;
		static bool offset_applied;

		/*
		 * note: trion == lucid, except for the prepare() op
		 * only apply the offsets once (in case of deferred probe)
		 */
		if (!offset_applied) {
			for (i = 0; i < ARRAY_SIZE(rcgs); i++)
				rcgs[i]->cmd_rcgr -= 4;

			for (i = 0; i < ARRAY_SIZE(divs); i++) {
				divs[i]->reg -= 4;
				divs[i]->width = 4;
			}

			disp_cc_mdss_ahb_clk.halt_reg -= 4;
			disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4;

			offset_applied = true;
		}

		disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0;

		disp_cc_pll0_config.config_ctl_hi1_val = 0x2a9a699c;
		disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000;
		disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
		disp_cc_pll0.vco_table = lucid_5lpe_vco;
		disp_cc_pll1_config.config_ctl_hi1_val = 0x2a9a699c;
		disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000;
		disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
		disp_cc_pll1.vco_table = lucid_5lpe_vco;

		disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK] = NULL;
		disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK_SRC] = NULL;
	}

	if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {
		clk_lucid_5lpe_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
		clk_lucid_5lpe_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
	} else {

Annotation

Implementation Notes