drivers/clk/qcom/mmcc-msm8996.c

Source file repositories/reference/linux-study-clean/drivers/clk/qcom/mmcc-msm8996.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/qcom/mmcc-msm8996.c
Extension
.c
Size
91227 bytes
Lines
3642
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*x
 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
 */

#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>

#include <dt-bindings/clock/qcom,mmcc-msm8996.h>

#include "common.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-alpha-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
#include "gdsc.h"

enum {
	P_XO,
	P_MMPLL0,
	P_GPLL0,
	P_GPLL0_DIV,
	P_MMPLL1,
	P_MMPLL9,
	P_MMPLL2,
	P_MMPLL8,
	P_MMPLL3,
	P_DSI0PLL,
	P_DSI1PLL,
	P_MMPLL5,
	P_HDMIPLL,
	P_DSI0PLL_BYTE,
	P_DSI1PLL_BYTE,
	P_MMPLL4,
};

static struct clk_fixed_factor gpll0_div = {
	.mult = 1,
	.div = 2,
	.hw.init = &(struct clk_init_data){
		.name = "gpll0_div",
		.parent_data = (const struct clk_parent_data[]){
			{ .fw_name = "gpll0", .name = "gpll0" },
		},
		.num_parents = 1,
		.ops = &clk_fixed_factor_ops,
	},
};

static const struct pll_vco mmpll_p_vco[] = {
	{ 250000000, 500000000, 3 },
	{ 500000000, 1000000000, 2 },
	{ 1000000000, 1500000000, 1 },
	{ 1500000000, 2000000000, 0 },
};

static const struct pll_vco mmpll_gfx_vco[] = {
	{ 400000000, 1000000000, 2 },
	{ 1000000000, 1500000000, 1 },
	{ 1500000000, 2000000000, 0 },
};

static const struct pll_vco mmpll_t_vco[] = {
	{ 500000000, 1500000000, 0 },
};

static struct clk_alpha_pll mmpll0_early = {
	.offset = 0x0,
	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
	.vco_table = mmpll_p_vco,
	.num_vco = ARRAY_SIZE(mmpll_p_vco),
	.clkr = {
		.enable_reg = 0x100,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
			.name = "mmpll0_early",
			.parent_data = (const struct clk_parent_data[]){
				{ .fw_name = "xo", .name = "xo_board" },
			},
			.num_parents = 1,
			.ops = &clk_alpha_pll_ops,
		},

Annotation

Implementation Notes