drivers/clk/qcom/nsscc-ipq5424.c

Source file repositories/reference/linux-study-clean/drivers/clk/qcom/nsscc-ipq5424.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/qcom/nsscc-ipq5424.c
Extension
.c
Size
37085 bytes
Lines
1341
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/interconnect-provider.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>

#include <dt-bindings/clock/qcom,ipq5424-nsscc.h>
#include <dt-bindings/interconnect/qcom,ipq5424.h>
#include <dt-bindings/reset/qcom,ipq5424-nsscc.h>

#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "reset.h"

/* Need to match the order of clocks in DT binding */
enum {
	DT_CMN_PLL_XO_CLK,
	DT_CMN_PLL_NSS_300M_CLK,
	DT_CMN_PLL_NSS_375M_CLK,
	DT_GCC_GPLL0_OUT_AUX,
	DT_UNIPHY0_NSS_RX_CLK,
	DT_UNIPHY0_NSS_TX_CLK,
	DT_UNIPHY1_NSS_RX_CLK,
	DT_UNIPHY1_NSS_TX_CLK,
	DT_UNIPHY2_NSS_RX_CLK,
	DT_UNIPHY2_NSS_TX_CLK,
};

enum {
	P_CMN_PLL_XO_CLK,
	P_CMN_PLL_NSS_300M_CLK,
	P_CMN_PLL_NSS_375M_CLK,
	P_GCC_GPLL0_OUT_AUX,
	P_UNIPHY0_NSS_RX_CLK,
	P_UNIPHY0_NSS_TX_CLK,
	P_UNIPHY1_NSS_RX_CLK,
	P_UNIPHY1_NSS_TX_CLK,
	P_UNIPHY2_NSS_RX_CLK,
	P_UNIPHY2_NSS_TX_CLK,
};

static const struct parent_map nss_cc_parent_map_0[] = {
	{ P_CMN_PLL_XO_CLK, 0 },
	{ P_GCC_GPLL0_OUT_AUX, 2 },
	{ P_CMN_PLL_NSS_300M_CLK, 5 },
	{ P_CMN_PLL_NSS_375M_CLK, 6 },
};

static const struct clk_parent_data nss_cc_parent_data_0[] = {
	{ .index = DT_CMN_PLL_XO_CLK },
	{ .index = DT_GCC_GPLL0_OUT_AUX },
	{ .index = DT_CMN_PLL_NSS_300M_CLK },
	{ .index = DT_CMN_PLL_NSS_375M_CLK },
};

static const struct parent_map nss_cc_parent_map_1[] = {
	{ P_CMN_PLL_XO_CLK, 0 },
	{ P_GCC_GPLL0_OUT_AUX, 2 },
	{ P_UNIPHY0_NSS_RX_CLK, 3 },
	{ P_UNIPHY0_NSS_TX_CLK, 4 },
	{ P_CMN_PLL_NSS_300M_CLK, 5 },
	{ P_CMN_PLL_NSS_375M_CLK, 6 },
};

static const struct clk_parent_data nss_cc_parent_data_1[] = {
	{ .index = DT_CMN_PLL_XO_CLK },
	{ .index = DT_GCC_GPLL0_OUT_AUX },
	{ .index = DT_UNIPHY0_NSS_RX_CLK },
	{ .index = DT_UNIPHY0_NSS_TX_CLK },
	{ .index = DT_CMN_PLL_NSS_300M_CLK },
	{ .index = DT_CMN_PLL_NSS_375M_CLK },
};

static const struct parent_map nss_cc_parent_map_2[] = {
	{ P_CMN_PLL_XO_CLK, 0 },

Annotation

Implementation Notes