drivers/clk/qcom/nsscc-ipq9574.c

Source file repositories/reference/linux-study-clean/drivers/clk/qcom/nsscc-ipq9574.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/qcom/nsscc-ipq9574.c
Extension
.c
Size
86737 bytes
Lines
3111
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
 * Copyright (c) 2023, 2025 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/interconnect-provider.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>

#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
#include <dt-bindings/interconnect/qcom,ipq9574.h>
#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>

#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "common.h"
#include "reset.h"

/* Need to match the order of clocks in DT binding */
enum {
	DT_XO,
	DT_BIAS_PLL_CC_CLK,
	DT_BIAS_PLL_UBI_NC_CLK,
	DT_GCC_GPLL0_OUT_AUX,
	DT_UNIPHY0_NSS_RX_CLK,
	DT_UNIPHY0_NSS_TX_CLK,
	DT_UNIPHY1_NSS_RX_CLK,
	DT_UNIPHY1_NSS_TX_CLK,
	DT_UNIPHY2_NSS_RX_CLK,
	DT_UNIPHY2_NSS_TX_CLK,
};

enum {
	P_XO,
	P_BIAS_PLL_CC_CLK,
	P_BIAS_PLL_UBI_NC_CLK,
	P_GCC_GPLL0_OUT_AUX,
	P_UBI32_PLL_OUT_MAIN,
	P_UNIPHY0_NSS_RX_CLK,
	P_UNIPHY0_NSS_TX_CLK,
	P_UNIPHY1_NSS_RX_CLK,
	P_UNIPHY1_NSS_TX_CLK,
	P_UNIPHY2_NSS_RX_CLK,
	P_UNIPHY2_NSS_TX_CLK,
};

static const struct alpha_pll_config ubi32_pll_config = {
	.l = 0x3e,
	.alpha = 0x6666,
	.config_ctl_val = 0x200d4aa8,
	.config_ctl_hi_val = 0x3c,
	.main_output_mask = BIT(0),
	.aux_output_mask = BIT(1),
	.pre_div_val = 0x0,
	.pre_div_mask = BIT(12),
	.post_div_val = 0x0,
	.post_div_mask = GENMASK(9, 8),
	.alpha_en_mask = BIT(24),
	.test_ctl_val = 0x1c0000c0,
	.test_ctl_hi_val = 0x4000,
};

static struct clk_alpha_pll ubi32_pll_main = {
	.offset = 0x28000,
	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
	.flags = SUPPORTS_DYNAMIC_UPDATE,
	.clkr = {
		.hw.init = &(const struct clk_init_data) {
			.name = "ubi32_pll_main",
			.parent_data = &(const struct clk_parent_data) {
				.index = DT_XO,
			},
			.num_parents = 1,
			.ops = &clk_alpha_pll_huayra_ops,
		},

Annotation

Implementation Notes