drivers/clk/qcom/nsscc-qca8k.c

Source file repositories/reference/linux-study-clean/drivers/clk/qcom/nsscc-qca8k.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/qcom/nsscc-qca8k.c
Extension
.c
Size
60727 bytes
Lines
2222
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <linux/clk-provider.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/phy.h>
#include <linux/mdio.h>
#include <linux/clk.h>
#include <linux/gpio/consumer.h>

#include <dt-bindings/clock/qcom,qca8k-nsscc.h>
#include <dt-bindings/reset/qcom,qca8k-nsscc.h>

#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "common.h"
#include "reset.h"

#define QCA8K_CLK_REG_BASE		0x800000
#define QCA8K_HIGH_ADDR_PREFIX		0x18
#define QCA8K_LOW_ADDR_PREFIX		0x10
#define QCA8K_CFG_PAGE_REG		0xc
#define QCA8K_CLK_REG_MASK		GENMASK(4, 0)
#define QCA8K_CLK_PHY_ADDR_MASK		GENMASK(7, 5)
#define QCA8K_CLK_PAGE_MASK		GENMASK(23, 8)
#define QCA8K_REG_DATA_UPPER_16_BITS	BIT(1)

enum {
	DT_XO,
	DT_UNIPHY0_RX_CLK,
	DT_UNIPHY0_TX_CLK,
	DT_UNIPHY1_RX_CLK,
	DT_UNIPHY1_TX_CLK,
	DT_UNIPHY1_RX312P5M_CLK,
	DT_UNIPHY1_TX312P5M_CLK,
};

enum {
	P_XO,
	P_UNIPHY0_RX,
	P_UNIPHY0_TX,
	P_UNIPHY1_RX,
	P_UNIPHY1_TX,
	P_UNIPHY1_RX312P5M,
	P_UNIPHY1_TX312P5M,
	P_MAC4_RX_DIV,
	P_MAC4_TX_DIV,
	P_MAC5_RX_DIV,
	P_MAC5_TX_DIV,
};

static const struct clk_parent_data nss_cc_uniphy1_tx312p5m_data[] = {
	{ .index = DT_XO },
	{ .index = DT_UNIPHY1_TX312P5M_CLK },
};

static const struct parent_map nss_cc_uniphy1_tx312p5m_map[] = {
	{ P_XO, 0 },
	{ P_UNIPHY1_TX312P5M, 1 },
};

static struct clk_rcg2 nss_cc_switch_core_clk_src = {
	.cmd_rcgr = 0x0,
	.hid_width = 5,
	.parent_map = nss_cc_uniphy1_tx312p5m_map,
	.clkr.hw.init = &(const struct clk_init_data) {
		.name = "nss_cc_switch_core_clk_src",
		.parent_data = nss_cc_uniphy1_tx312p5m_data,
		.num_parents = ARRAY_SIZE(nss_cc_uniphy1_tx312p5m_data),
		.ops = &clk_rcg2_mux_closest_ops,
	},
};

static struct clk_branch nss_cc_switch_core_clk = {
	.halt_reg = 0x8,
	.halt_check = BRANCH_HALT,
	.clkr = {
		.enable_reg = 0x8,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
			.name = "nss_cc_switch_core_clk",
			.parent_hws = (const struct clk_hw *[]) {

Annotation

Implementation Notes