drivers/clk/renesas/r7s9210-cpg-mssr.c

Source file repositories/reference/linux-study-clean/drivers/clk/renesas/r7s9210-cpg-mssr.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/renesas/r7s9210-cpg-mssr.c
Extension
.c
Size
6008 bytes
Lines
226
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

switch (r7s9210_core_clks[i].id) {
		case R7S9210_CLK_I:
			r7s9210_core_clks[i].div = ratio_tab[index].i;
			break;
		case R7S9210_CLK_G:
			r7s9210_core_clks[i].div = ratio_tab[index].g;
			break;
		case R7S9210_CLK_B:
			r7s9210_core_clks[i].div = ratio_tab[index].b;
			break;
		case R7S9210_CLK_P1:
		case R7S9210_CLK_P1C:
			r7s9210_core_clks[i].div = ratio_tab[index].p1;
			break;
		case R7S9210_CLK_P0:
			r7s9210_core_clks[i].div = 32;
			break;
		}
	}
}

static struct clk * __init rza2_cpg_clk_register(struct device *dev,
	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
	struct cpg_mssr_pub *pub)
{
	void __iomem *base = pub->base0;
	struct clk **clks = pub->clks;
	unsigned int mult = 1;
	unsigned int div = 1;
	struct clk *parent;

	parent = clks[core->parent];
	if (IS_ERR(parent))
		return ERR_CAST(parent);

	switch (core->type) {
	case CLK_TYPE_RZA_MAIN:
		r7s9210_update_clk_table(parent, base);
		break;

	case CLK_TYPE_RZA_PLL:
		if (cpg_mode)
			mult = 44;	/* Divider 1 is 1/2 */
		else
			mult = 88;	/* Divider 1 is 1 */
		break;

	default:
		return ERR_PTR(-EINVAL);
	}

	return clk_register_fixed_factor(NULL, core->name,
					 __clk_get_name(parent), 0, mult, div);
}

const struct cpg_mssr_info r7s9210_cpg_mssr_info __initconst = {
	/* Early Clocks */
	.early_core_clks = r7s9210_early_core_clks,
	.num_early_core_clks = ARRAY_SIZE(r7s9210_early_core_clks),
	.early_mod_clks = r7s9210_early_mod_clks,
	.num_early_mod_clks = ARRAY_SIZE(r7s9210_early_mod_clks),

	/* Core Clocks */
	.core_clks = r7s9210_core_clks,
	.num_core_clks = ARRAY_SIZE(r7s9210_core_clks),
	.last_dt_core_clk = LAST_DT_CORE_CLK,
	.num_total_core_clks = MOD_CLK_BASE,

	/* Module Clocks */
	.mod_clks = r7s9210_mod_clks,
	.num_mod_clks = ARRAY_SIZE(r7s9210_mod_clks),
	.num_hw_mod_clks = 11 * 32, /* includes STBCR0 which doesn't exist */

	/* Callbacks */
	.cpg_clk_register = rza2_cpg_clk_register,

	/* RZ/A2 has Standby Control Registers */
	.reg_layout = CLK_REG_LAYOUT_RZ_A,
};

static void __init r7s9210_cpg_mssr_early_init(struct device_node *np)
{
	cpg_mssr_early_init(np, &r7s9210_cpg_mssr_info);
}

CLK_OF_DECLARE_DRIVER(cpg_mstp_clks, "renesas,r7s9210-cpg-mssr",
		      r7s9210_cpg_mssr_early_init);

Annotation

Implementation Notes