drivers/clk/renesas/r8a7792-cpg-mssr.c

Source file repositories/reference/linux-study-clean/drivers/clk/renesas/r8a7792-cpg-mssr.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/renesas/r8a7792-cpg-mssr.c
Extension
.c
Size
7937 bytes
Lines
228
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * r8a7792 Clock Pulse Generator / Module Standby and Software Reset
 *
 * Copyright (C) 2017 Glider bvba
 *
 * Based on clk-rcar-gen2.c
 *
 * Copyright (C) 2013 Ideas On Board SPRL
 */

#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/soc/renesas/rcar-rst.h>

#include <dt-bindings/clock/r8a7792-cpg-mssr.h>

#include "renesas-cpg-mssr.h"
#include "rcar-gen2-cpg.h"

enum clk_ids {
	/* Core Clock Outputs exported to DT */
	LAST_DT_CORE_CLK = R8A7792_CLK_OSC,

	/* External Input Clocks */
	CLK_EXTAL,

	/* Internal Core Clocks */
	CLK_MAIN,
	CLK_PLL0,
	CLK_PLL1,
	CLK_PLL3,
	CLK_PLL1_DIV2,

	/* Module Clocks */
	MOD_CLK_BASE
};

static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
	/* External Clock Inputs */
	DEF_INPUT("extal",     CLK_EXTAL),

	/* Internal Core Clocks */
	DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
	DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
	DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
	DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),

	DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),

	/* Core Clock Outputs */
	DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),

	DEF_FIXED("z",      R8A7792_CLK_Z,     CLK_PLL0,          1, 1),
	DEF_FIXED("zg",     R8A7792_CLK_ZG,    CLK_PLL1,          5, 1),
	DEF_FIXED("zx",     R8A7792_CLK_ZX,    CLK_PLL1,          3, 1),
	DEF_FIXED("zs",     R8A7792_CLK_ZS,    CLK_PLL1,          6, 1),
	DEF_FIXED("hp",     R8A7792_CLK_HP,    CLK_PLL1,         12, 1),
	DEF_FIXED("i",      R8A7792_CLK_I,     CLK_PLL1,          3, 1),
	DEF_FIXED("b",      R8A7792_CLK_B,     CLK_PLL1,         12, 1),
	DEF_FIXED("lb",     R8A7792_CLK_LB,    CLK_PLL1,         24, 1),
	DEF_FIXED("p",      R8A7792_CLK_P,     CLK_PLL1,         24, 1),
	DEF_FIXED("cl",     R8A7792_CLK_CL,    CLK_PLL1,         48, 1),
	DEF_FIXED("m2",     R8A7792_CLK_M2,    CLK_PLL1,          8, 1),
	DEF_FIXED("imp",    R8A7792_CLK_IMP,   CLK_PLL1,          4, 1),
	DEF_FIXED("zb3",    R8A7792_CLK_ZB3,   CLK_PLL3,          4, 1),
	DEF_FIXED("zb3d2",  R8A7792_CLK_ZB3D2, CLK_PLL3,          8, 1),
	DEF_FIXED("ddr",    R8A7792_CLK_DDR,   CLK_PLL3,          8, 1),
	DEF_FIXED("sd",     R8A7792_CLK_SD,    CLK_PLL1_DIV2,     8, 1),
	DEF_FIXED("mp",     R8A7792_CLK_MP,    CLK_PLL1_DIV2,    15, 1),
	DEF_FIXED("cp",     R8A7792_CLK_CP,    CLK_PLL1,         48, 1),
	DEF_FIXED("cpex",   R8A7792_CLK_CPEX,  CLK_EXTAL,         2, 1),
	DEF_FIXED("rcan",   R8A7792_CLK_RCAN,  CLK_PLL1_DIV2,    49, 1),
	DEF_FIXED("r",      R8A7792_CLK_R,     CLK_PLL1,      49152, 1),
	DEF_FIXED("osc",    R8A7792_CLK_OSC,   CLK_PLL1,      12288, 1),
};

static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
	DEF_MOD("msiof0",		   0,	R8A7792_CLK_MP),
	DEF_MOD("jpu",			 106,	R8A7792_CLK_M2),
	DEF_MOD("tmu1",			 111,	R8A7792_CLK_P),
	DEF_MOD("3dg",			 112,	R8A7792_CLK_ZG),
	DEF_MOD("2d-dmac",		 115,	R8A7792_CLK_ZS),
	DEF_MOD("tmu3",			 121,	R8A7792_CLK_P),
	DEF_MOD("tmu2",			 122,	R8A7792_CLK_P),
	DEF_MOD("cmt0",			 124,	R8A7792_CLK_R),
	DEF_MOD("tmu0",			 125,	R8A7792_CLK_CP),
	DEF_MOD("vsp1du1",		 127,	R8A7792_CLK_ZS),
	DEF_MOD("vsp1du0",		 128,	R8A7792_CLK_ZS),

Annotation

Implementation Notes