drivers/clk/renesas/r9a08g046-cpg.c

Source file repositories/reference/linux-study-clean/drivers/clk/renesas/r9a08g046-cpg.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/renesas/r9a08g046-cpg.c
Extension
.c
Size
4592 bytes
Lines
154
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * RZ/G3L CPG driver
 *
 * Copyright (C) 2026 Renesas Electronics Corp.
 */

#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>

#include <dt-bindings/clock/renesas,r9a08g046-cpg.h>

#include "rzg2l-cpg.h"

/* RZ/G3L Specific registers. */
#define G3L_CPG_PL2_DDIV		(0x204)
#define G3L_CPG_PL3_DDIV		(0x208)
#define G3L_CLKDIVSTATUS		(0x280)

/* RZ/G3L Specific division configuration.  */
#define G3L_DIVPL2A		DDIV_PACK(G3L_CPG_PL2_DDIV, 0, 2)
#define G3L_DIVPL2B		DDIV_PACK(G3L_CPG_PL2_DDIV, 4, 2)
#define G3L_DIVPL3A		DDIV_PACK(G3L_CPG_PL3_DDIV, 0, 2)

/* RZ/G3L Clock status configuration. */
#define G3L_DIVPL2A_STS		DDIV_PACK(G3L_CLKDIVSTATUS, 4, 1)
#define G3L_DIVPL2B_STS		DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1)
#define G3L_DIVPL3A_STS		DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1)

enum clk_ids {
	/* Core Clock Outputs exported to DT */
	LAST_DT_CORE_CLK = R9A08G046_USB_SCLK,

	/* External Input Clocks */
	CLK_EXTAL,
	CLK_ETH0_TXC_TX_CLK_IN,
	CLK_ETH0_RXC_RX_CLK_IN,
	CLK_ETH1_TXC_TX_CLK_IN,
	CLK_ETH1_RXC_RX_CLK_IN,

	/* Internal Core Clocks */
	CLK_PLL2,
	CLK_PLL2_DIV2,
	CLK_PLL3,
	CLK_PLL3_DIV2,

	/* Module Clocks */
	MOD_CLK_BASE,
};

/* Divider tables */
static const struct clk_div_table dtable_4_128[] = {
	{ 0, 4 },
	{ 1, 8 },
	{ 2, 16 },
	{ 3, 128 },
	{ 0, 0 },
};

static const struct clk_div_table dtable_8_256[] = {
	{ 0, 8 },
	{ 1, 16 },
	{ 2, 32 },
	{ 3, 256 },
	{ 0, 0 },
};

static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = {
	/* External Clock Inputs */
	DEF_INPUT("extal", CLK_EXTAL),
	DEF_INPUT("eth0_txc_tx_clk", CLK_ETH0_TXC_TX_CLK_IN),
	DEF_INPUT("eth0_rxc_rx_clk", CLK_ETH0_RXC_RX_CLK_IN),
	DEF_INPUT("eth1_txc_tx_clk", CLK_ETH1_TXC_TX_CLK_IN),
	DEF_INPUT("eth1_rxc_rx_clk", CLK_ETH1_RXC_RX_CLK_IN),

	/* Internal Core Clocks */
	DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
	DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
	DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
	DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),

	/* Core output clk */
	DEF_G3S_DIV("P0", R9A08G046_CLK_P0, CLK_PLL2_DIV2, G3L_DIVPL2B, G3L_DIVPL2B_STS,
		    dtable_8_256, 0, 0, 0, NULL),
	DEF_G3S_DIV("P1", R9A08G046_CLK_P1, CLK_PLL3_DIV2, G3L_DIVPL3A, G3L_DIVPL3A_STS,
		    dtable_4_128, 0, 0, 0, NULL),
	DEF_G3S_DIV("P3", R9A08G046_CLK_P3, CLK_PLL2_DIV2, G3L_DIVPL2A, G3L_DIVPL2A_STS,
		    dtable_4_128, 0, 0, 0, NULL),

Annotation

Implementation Notes