drivers/clk/renesas/r9a09g011-cpg.c

Source file repositories/reference/linux-study-clean/drivers/clk/renesas/r9a09g011-cpg.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/renesas/r9a09g011-cpg.c
Extension
.c
Size
10104 bytes
Lines
269
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * RZ/V2M Clock Pulse Generator / Module Standby and Software Reset
 *
 * Copyright (C) 2022 Renesas Electronics Corp.
 *
 * Based on r9a07g044-cpg.c
 */

#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>

#include <dt-bindings/clock/r9a09g011-cpg.h>

#include "rzg2l-cpg.h"

#define RZV2M_SAMPLL4_CLK1	0x104
#define RZV2M_SAMPLL4_CLK2	0x108

#define PLL4_CONF	(RZV2M_SAMPLL4_CLK1 << 22 | RZV2M_SAMPLL4_CLK2 << 12)

#define DIV_A		DDIV_PACK(0x200, 0, 3)
#define DIV_B		DDIV_PACK(0x204, 0, 2)
#define DIV_D		DDIV_PACK(0x204, 4, 2)
#define DIV_E		DDIV_PACK(0x204, 8, 1)
#define DIV_W		DDIV_PACK(0x328, 0, 3)

#define SEL_B		SEL_PLL_PACK(0x214, 0, 1)
#define SEL_CSI0	SEL_PLL_PACK(0x330, 0, 1)
#define SEL_CSI4	SEL_PLL_PACK(0x330, 4, 1)
#define SEL_D		SEL_PLL_PACK(0x214, 1, 1)
#define SEL_E		SEL_PLL_PACK(0x214, 2, 1)
#define SEL_SDI		SEL_PLL_PACK(0x300, 0, 1)
#define SEL_W0		SEL_PLL_PACK(0x32C, 0, 1)

enum clk_ids {
	/* Core Clock Outputs exported to DT */
	LAST_DT_CORE_CLK = 0,

	/* External Input Clocks */
	CLK_EXTAL,

	/* Internal Core Clocks */
	CLK_MAIN,
	CLK_MAIN_24,
	CLK_MAIN_2,
	CLK_PLL1,
	CLK_PLL2,
	CLK_PLL2_800,
	CLK_PLL2_400,
	CLK_PLL2_200,
	CLK_PLL2_100,
	CLK_PLL4,
	CLK_DIV_A,
	CLK_DIV_B,
	CLK_DIV_D,
	CLK_DIV_E,
	CLK_DIV_W,
	CLK_SEL_B,
	CLK_SEL_B_D2,
	CLK_SEL_CSI0,
	CLK_SEL_CSI4,
	CLK_SEL_D,
	CLK_SEL_E,
	CLK_SEL_SDI,
	CLK_SEL_W0,

	/* Module Clocks */
	MOD_CLK_BASE
};

/* Divider tables */
static const struct clk_div_table dtable_diva[] = {
	{0, 1},
	{1, 2},
	{2, 3},
	{3, 4},
	{4, 6},
	{5, 12},
	{6, 24},
	{0, 0},
};

static const struct clk_div_table dtable_divb[] = {
	{0, 1},
	{1, 2},
	{2, 4},
	{3, 8},

Annotation

Implementation Notes