drivers/clk/renesas/renesas-cpg-mssr.h

Source file repositories/reference/linux-study-clean/drivers/clk/renesas/renesas-cpg-mssr.h

File Facts

System
Linux kernel
Corpus path
drivers/clk/renesas/renesas-cpg-mssr.h
Extension
.h
Size
7465 bytes
Lines
223
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct cpg_core_clk {
	/* Common */
	const char *name;
	unsigned int id;
	unsigned int type;
	/* Depending on type */
	unsigned int parent;	/* Core Clocks only */
	unsigned int div;
	unsigned int mult;
	unsigned int offset;
	union {
		const char * const *parent_names;
		const struct clk_div_table *dtable;
	};
	u32 conf;
	u16 flag;
	u8 mux_flags;
	u8 num_parents;
};

/**
 * struct cpg_mssr_pub - data shared with device-specific clk registration code
 *
 * @base0: CPG/MSSR register block base0 address
 * @base1: CPG/MSSR register block base1 address
 * @notifiers: Notifier chain to save/restore clock state for system resume
 * @rmw_lock: protects RMW register accesses
 * @clks: pointer to clocks
 */
struct cpg_mssr_pub {
	void __iomem *base0;
	void __iomem *base1;
	struct raw_notifier_head notifiers;
	spinlock_t rmw_lock;
	struct clk **clks;
};

enum clk_types {
	/* Generic */
	CLK_TYPE_IN,		/* External Clock Input */
	CLK_TYPE_FF,		/* Fixed Factor Clock */
	CLK_TYPE_DIV6P1,	/* DIV6 Clock with 1 parent clock */
	CLK_TYPE_DIV6_RO,	/* DIV6 Clock read only with extra divisor */
	CLK_TYPE_FR,		/* Fixed Rate Clock */

	/* Custom definitions start here */
	CLK_TYPE_CUSTOM,
};

#define DEF_TYPE(_name, _id, _type...)	\
	{ .name = _name, .id = _id, .type = _type }
#define DEF_BASE(_name, _id, _type, _parent...)	\
	DEF_TYPE(_name, _id, _type, .parent = _parent)

#define DEF_INPUT(_name, _id) \
	DEF_TYPE(_name, _id, CLK_TYPE_IN)
#define DEF_FIXED(_name, _id, _parent, _div, _mult)	\
	DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
#define DEF_DIV6P1(_name, _id, _parent, _offset)	\
	DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div)	\
	DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
#define DEF_RATE(_name, _id, _rate)	\
	DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)

    /*
     * Definitions of Module Clocks
     */

struct mssr_mod_clk {
	const char *name;
	unsigned int id;
	unsigned int parent;	/* Add MOD_CLK_BASE for Module Clocks */
};

/* Convert from sparse base-100 to packed index space */
#define MOD_CLK_PACK(x)	((x) - ((x) / 100) * (100 - 32))

#define MOD_CLK_ID(x)	(MOD_CLK_BASE + MOD_CLK_PACK(x))

#define DEF_MOD(_name, _mod, _parent...)	\
	{ .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }

/* Convert from sparse base-10 to packed index space */
#define MOD_CLK_PACK_10(x)	((x / 10) * 32 + (x % 10))

#define MOD_CLK_ID_10(x)	(MOD_CLK_BASE + MOD_CLK_PACK_10(x))

#define DEF_MOD_STB(_name, _mod, _parent...)	\
	{ .name = _name, .id = MOD_CLK_ID_10(_mod), .parent = _parent }

Annotation

Implementation Notes