drivers/clk/renesas/rzg2l-cpg.c

File Facts

System

Linux kernel

Corpus path

drivers/clk/renesas/rzg2l-cpg.c

Extension

.c

Size

56888 bytes

Lines

2186

Domain

Driver Families

Bucket

drivers/clk

Inferred role

Driver Families: exported/initcall integration point

Status

integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
• Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
• Allocates kernel memory; connect allocation flags and lifetime to context constraints.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/atomic.h
• linux/bitfield.h
• linux/cleanup.h
• linux/clk.h
• linux/clk-provider.h
• linux/clk/renesas.h
• linux/debugfs.h
• linux/delay.h
• linux/device.h
• linux/init.h
• linux/iopoll.h
• linux/math64.h
• linux/mod_devicetable.h
• linux/module.h
• linux/of.h
• linux/platform_device.h
• linux/pm_clock.h
• linux/pm_domain.h
• linux/reset-controller.h
• linux/slab.h
• linux/string_choices.h
• linux/units.h
• dt-bindings/clock/renesas-cpg-mssr.h
• rzg2l-cpg.h

Detected Declarations

• struct clk_hw_data
• struct sd_mux_hw_data
• struct div_hw_data
• struct rzg2l_pll5_param
• struct rzg2l_pll5_mux_dsi_div_param
• struct rzg2l_cpg_priv
• struct dsi_div_hw_data
• struct pll5_mux_hw_data
• struct sipll5
• struct pll_clk
• struct mstop
• struct mod_clock
• function rzg2l_cpg_div_ab
• function rzg2l_cpg_del_clk_provider
• function rzg2l_cpg_wait_clk_update_done
• function rzg2l_cpg_sd_clk_mux_notifier
• function rzg3s_cpg_div_clk_notifier
• function function
• function rzg2l_register_notifier
• function rzg3s_div_clk_recalc_rate
• function rzg3s_div_clk_determine_rate
• function rzg3s_div_clk_set_rate
• function rzg3s_cpg_div_clk_register
• function rzg2l_cpg_div_clk_register
• function rzg2l_cpg_mux_clk_register
• function rzg2l_cpg_sd_clk_mux_set_parent
• function rzg2l_cpg_sd_clk_mux_get_parent
• function rzg2l_cpg_sd_mux_clk_register
• function rzg2l_cpg_get_foutpostdiv_rate
• function rzg2l_cpg_dsi_div_recalc_rate
• function rzg2l_cpg_get_vclk_parent_rate
• function rzg2l_cpg_dsi_div_determine_rate
• function rzg2l_cpg_dsi_div_set_divider
• function rzg2l_cpg_dsi_div_set_rate
• function rzg2l_cpg_dsi_div_clk_register
• function rzg2l_cpg_pll5_4_clk_mux_determine_rate
• function rzg2l_cpg_pll5_4_clk_mux_set_parent
• function rzg2l_cpg_pll5_4_clk_mux_get_parent
• function rzg2l_cpg_pll5_4_mux_clk_register
• function rzg2l_cpg_sipll5_recalc_rate
• function rzg2l_cpg_sipll5_determine_rate
• function rzg2l_cpg_sipll5_set_rate
• function rzg2l_cpg_sipll5_register
• function rzg2l_cpg_pll_clk_recalc_rate
• function rzg3s_cpg_pll_clk_recalc_rate
• function rzg2l_cpg_pll_clk_register
• function rzg2l_cpg_register_core_clk
• function rzg2l_mod_clock_mstop_show

Annotated Snippet

subsys_initcall(rzg2l_cpg_init);

MODULE_DESCRIPTION("Renesas RZ/G2L CPG Driver");

Annotation

• Immediate include surface: `linux/atomic.h`, `linux/bitfield.h`, `linux/cleanup.h`, `linux/clk.h`, `linux/clk-provider.h`, `linux/clk/renesas.h`, `linux/debugfs.h`, `linux/delay.h`.
• Detected declarations: `struct clk_hw_data`, `struct sd_mux_hw_data`, `struct div_hw_data`, `struct rzg2l_pll5_param`, `struct rzg2l_pll5_mux_dsi_div_param`, `struct rzg2l_cpg_priv`, `struct dsi_div_hw_data`, `struct pll5_mux_hw_data`, `struct sipll5`, `struct pll_clk`.
• Atlas domain: Driver Families / drivers/clk.
• Implementation status: integration implementation candidate.
• Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.