drivers/clk/renesas/rzv2h-cpg.c

File Facts

System

Linux kernel

Corpus path

drivers/clk/renesas/rzv2h-cpg.c

Extension

.c

Size

45554 bytes

Lines

1695

Domain

Driver Families

Bucket

drivers/clk

Inferred role

Driver Families: exported/initcall integration point

Status

integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
• Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
• Allocates kernel memory; connect allocation flags and lifetime to context constraints.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/bitfield.h
• linux/clk.h
• linux/clk-provider.h
• linux/clk/renesas.h
• linux/delay.h
• linux/init.h
• linux/iopoll.h
• linux/limits.h
• linux/math.h
• linux/math64.h
• linux/minmax.h
• linux/mod_devicetable.h
• linux/module.h
• linux/of.h
• linux/platform_device.h
• linux/pm_clock.h
• linux/pm_domain.h
• linux/refcount.h
• linux/reset-controller.h
• linux/string_choices.h
• linux/units.h
• dt-bindings/clock/renesas-cpg-mssr.h
• rzv2h-cpg.h

Detected Declarations

• struct rzv2h_pll_dsi_info
• struct rzv2h_cpg_priv
• struct pll_clk
• struct mod_clock
• struct ddiv_clk
• struct rzv2h_ff_mod_status_clk
• struct rzv2h_plldsi_div_clk
• struct rzv2h_cpg_pd
• function parameters
• function parameters
• function rzv2h_cpg_plldsi_div_recalc_rate
• function rzv2h_cpg_plldsi_div_determine_rate
• function rzv2h_cpg_plldsi_div_set_rate
• function rzv2h_cpg_plldsi_div_clk_register
• function rzv2h_cpg_plldsi_determine_rate
• function rzv2h_cpg_pll_set_rate
• function rzv2h_cpg_plldsi_set_rate
• function rzv2h_cpg_pll_clk_is_enabled
• function rzv2h_cpg_pll_clk_enable
• function rzv2h_cpg_pll_clk_recalc_rate
• function rzv2h_cpg_pll_clk_register
• function rzv2h_ddiv_recalc_rate
• function rzv2h_ddiv_determine_rate
• function rzv2h_cpg_wait_ddiv_clk_update_done
• function rzv2h_ddiv_set_rate
• function rzv2h_cpg_ddiv_clk_register
• function rzv2h_cpg_mux_clk_register
• function rzv2h_clk_ff_mod_status_is_enabled
• function rzv2h_cpg_fixed_mod_status_clk_register
• function rzv2h_cpg_register_core_clk
• function rzv2h_mod_clock_mstop_enable
• function rzv2h_mod_clock_mstop_disable
• function rzv2h_parent_clk_mux_to_index
• function rzv2h_mod_clock_is_enabled
• function rzv2h_mod_clock_endisable
• function rzv2h_mod_clock_enable
• function rzv2h_mod_clock_disable
• function rzv2h_cpg_register_mod_clk
• function for_each_set_bit
• function __rzv2h_cpg_assert
• function rzv2h_cpg_assert
• function rzv2h_cpg_deassert
• function rzv2h_cpg_reset
• function rzv2h_cpg_status
• function rzv2h_cpg_reset_xlate
• function rzv2h_cpg_reset_controller_register
• function rzv2h_cpg_is_pm_clk
• function rzv2h_cpg_attach_dev

Annotated Snippet

subsys_initcall(rzv2h_cpg_init);

MODULE_DESCRIPTION("Renesas RZ/V2H CPG Driver");

Annotation

• Immediate include surface: `linux/bitfield.h`, `linux/clk.h`, `linux/clk-provider.h`, `linux/clk/renesas.h`, `linux/delay.h`, `linux/init.h`, `linux/iopoll.h`, `linux/limits.h`.
• Detected declarations: `struct rzv2h_pll_dsi_info`, `struct rzv2h_cpg_priv`, `struct pll_clk`, `struct mod_clock`, `struct ddiv_clk`, `struct rzv2h_ff_mod_status_clk`, `struct rzv2h_plldsi_div_clk`, `struct rzv2h_cpg_pd`, `function parameters`, `function parameters`.
• Atlas domain: Driver Families / drivers/clk.
• Implementation status: integration implementation candidate.
• Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.