drivers/clk/renesas/rzv2h-cpg.h
Source file repositories/reference/linux-study-clean/drivers/clk/renesas/rzv2h-cpg.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/clk/renesas/rzv2h-cpg.h- Extension
.h- Size
- 11072 bytes
- Lines
- 369
- Domain
- Driver Families
- Bucket
- drivers/clk
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitfield.hlinux/types.h
Detected Declarations
struct pllstruct ddivstruct smuxedstruct fixed_mod_confstruct cpg_core_clkstruct rzv2h_mod_clkstruct rzv2h_resetstruct rzv2h_cpg_infoenum clk_types
Annotated Snippet
struct pll {
unsigned int offset:9;
unsigned int has_clkn:1;
unsigned int instance:2;
const struct rzv2h_pll_limits *limits;
};
#define PLL_PACK_LIMITS(_offset, _has_clkn, _instance, _limits) \
((struct pll){ \
.offset = _offset, \
.has_clkn = _has_clkn, \
.instance = _instance, \
.limits = _limits \
})
#define PLL_PACK(_offset, _has_clkn, _instance) \
PLL_PACK_LIMITS(_offset, _has_clkn, _instance, NULL)
#define PLLCA55 PLL_PACK(0x60, 1, 0)
#define PLLGPU PLL_PACK(0x120, 1, 0)
/**
* struct ddiv - Structure for dynamic switching divider
*
* @offset: register offset
* @shift: position of the divider bit
* @width: width of the divider
* @monbit: monitor bit in CPG_CLKSTATUS0 register
* @no_rmw: flag to indicate if the register is read-modify-write
* (1: no RMW, 0: RMW)
*/
struct ddiv {
unsigned int offset:11;
unsigned int shift:4;
unsigned int width:4;
unsigned int monbit:5;
unsigned int no_rmw:1;
};
/*
* On RZ/V2H(P), the dynamic divider clock supports up to 19 monitor bits,
* while on RZ/G3E, it supports up to 16 monitor bits. Use the maximum value
* `0x1f` to indicate that monitor bits are not supported for static divider
* clocks.
*/
#define CSDIV_NO_MON (0x1f)
#define DDIV_PACK(_offset, _shift, _width, _monbit) \
((struct ddiv){ \
.offset = _offset, \
.shift = _shift, \
.width = _width, \
.monbit = _monbit \
})
#define DDIV_PACK_NO_RMW(_offset, _shift, _width, _monbit) \
((struct ddiv){ \
.offset = (_offset), \
.shift = (_shift), \
.width = (_width), \
.monbit = (_monbit), \
.no_rmw = 1 \
})
/**
* struct smuxed - Structure for static muxed clocks
*
* @offset: register offset
* @shift: position of the divider field
* @width: width of the divider field
*/
struct smuxed {
unsigned int offset:11;
unsigned int shift:4;
unsigned int width:4;
};
#define SMUX_PACK(_offset, _shift, _width) \
((struct smuxed){ \
.offset = (_offset), \
.shift = (_shift), \
.width = (_width), \
})
/**
* struct fixed_mod_conf - Structure for fixed module configuration
*
* @mon_index: monitor index
* @mon_bit: monitor bit
*/
Annotation
- Immediate include surface: `linux/bitfield.h`, `linux/types.h`.
- Detected declarations: `struct pll`, `struct ddiv`, `struct smuxed`, `struct fixed_mod_conf`, `struct cpg_core_clk`, `struct rzv2h_mod_clk`, `struct rzv2h_reset`, `struct rzv2h_cpg_info`, `enum clk_types`.
- Atlas domain: Driver Families / drivers/clk.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.