drivers/clk/rockchip/clk-muxgrf.c
Source file repositories/reference/linux-study-clean/drivers/clk/rockchip/clk-muxgrf.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/clk/rockchip/clk-muxgrf.c- Extension
.c- Size
- 2237 bytes
- Lines
- 93
- Domain
- Driver Families
- Bucket
- drivers/clk
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/slab.hlinux/bitops.hlinux/regmap.hlinux/clk.hlinux/clk-provider.hclk.h
Detected Declarations
struct rockchip_muxgrf_clockfunction rockchip_muxgrf_get_parentfunction rockchip_muxgrf_set_parent
Annotated Snippet
struct rockchip_muxgrf_clock {
struct clk_hw hw;
struct regmap *regmap;
u32 reg;
u32 shift;
u32 width;
int flags;
};
#define to_muxgrf_clock(_hw) container_of(_hw, struct rockchip_muxgrf_clock, hw)
static u8 rockchip_muxgrf_get_parent(struct clk_hw *hw)
{
struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw);
unsigned int mask = GENMASK(mux->width - 1, 0);
unsigned int val;
regmap_read(mux->regmap, mux->reg, &val);
val >>= mux->shift;
val &= mask;
return val;
}
static int rockchip_muxgrf_set_parent(struct clk_hw *hw, u8 index)
{
struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw);
unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
unsigned int val;
val = index;
val <<= mux->shift;
if (mux->flags & CLK_MUX_HIWORD_MASK)
return regmap_write(mux->regmap, mux->reg, val | (mask << 16));
else
return regmap_update_bits(mux->regmap, mux->reg, mask, val);
}
static const struct clk_ops rockchip_muxgrf_clk_ops = {
.get_parent = rockchip_muxgrf_get_parent,
.set_parent = rockchip_muxgrf_set_parent,
.determine_rate = __clk_mux_determine_rate,
};
struct clk *rockchip_clk_register_muxgrf(const char *name,
const char *const *parent_names, u8 num_parents,
int flags, struct regmap *regmap, int reg,
int shift, int width, int mux_flags)
{
struct rockchip_muxgrf_clock *muxgrf_clock;
struct clk_init_data init;
struct clk *clk;
if (IS_ERR(regmap)) {
pr_err("%s: regmap not available\n", __func__);
return ERR_PTR(-ENOTSUPP);
}
muxgrf_clock = kmalloc_obj(*muxgrf_clock);
if (!muxgrf_clock)
return ERR_PTR(-ENOMEM);
init.name = name;
init.flags = flags;
init.num_parents = num_parents;
init.parent_names = parent_names;
init.ops = &rockchip_muxgrf_clk_ops;
muxgrf_clock->hw.init = &init;
muxgrf_clock->regmap = regmap;
muxgrf_clock->reg = reg;
muxgrf_clock->shift = shift;
muxgrf_clock->width = width;
muxgrf_clock->flags = mux_flags;
clk = clk_register(NULL, &muxgrf_clock->hw);
if (IS_ERR(clk))
kfree(muxgrf_clock);
return clk;
}
Annotation
- Immediate include surface: `linux/slab.h`, `linux/bitops.h`, `linux/regmap.h`, `linux/clk.h`, `linux/clk-provider.h`, `clk.h`.
- Detected declarations: `struct rockchip_muxgrf_clock`, `function rockchip_muxgrf_get_parent`, `function rockchip_muxgrf_set_parent`.
- Atlas domain: Driver Families / drivers/clk.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.