drivers/clk/rockchip/clk-rk3528.c

Source file repositories/reference/linux-study-clean/drivers/clk/rockchip/clk-rk3528.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/rockchip/clk-rk3528.c
Extension
.c
Size
50956 bytes
Lines
1188
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
 * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
 * Author: Joseph Chen <chenjh@rock-chips.com>
 */

#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/mfd/syscon.h>
#include <linux/minmax.h>
#include <linux/slab.h>

#include <dt-bindings/clock/rockchip,rk3528-cru.h>

#include "clk.h"

#define RK3528_GRF_SOC_STATUS0		0x1a0

enum rk3528_plls {
	apll, cpll, gpll, ppll, dpll,
};

static struct rockchip_pll_rate_table rk3528_pll_rates[] = {
	RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
	RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
	RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
	RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
	RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
	RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
	RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
	RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
	RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),		/* GPLL */
	RK3036_PLL_RATE(1092000000, 2, 91, 1, 1, 1, 0),
	RK3036_PLL_RATE(1008000000, 1, 42, 1, 1, 1, 0),
	RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0),	/* PPLL */
	RK3036_PLL_RATE(996000000, 2, 83, 1, 1, 1, 0),		/* CPLL */
	RK3036_PLL_RATE(960000000, 1, 40, 1, 1, 1, 0),
	RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
	RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
	RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0),
	RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
	RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
	RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
	RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
	RK3036_PLL_RATE(96000000, 1, 24, 3, 2, 1, 0),
	{ /* sentinel */ },
};

#define RK3528_DIV_ACLK_M_CORE_MASK	0x1f
#define RK3528_DIV_ACLK_M_CORE_SHIFT	11
#define RK3528_DIV_PCLK_DBG_MASK	0x1f
#define RK3528_DIV_PCLK_DBG_SHIFT	1

#define RK3528_CLKSEL39(_aclk_m_core)					\
{									\
	.reg = RK3528_CLKSEL_CON(39),					\
	.val = HIWORD_UPDATE(_aclk_m_core, RK3528_DIV_ACLK_M_CORE_MASK,	\
			     RK3528_DIV_ACLK_M_CORE_SHIFT),		\
}

#define RK3528_CLKSEL40(_pclk_dbg)					\
{									\
	.reg = RK3528_CLKSEL_CON(40),					\
	.val = HIWORD_UPDATE(_pclk_dbg, RK3528_DIV_PCLK_DBG_MASK,	\
			     RK3528_DIV_PCLK_DBG_SHIFT),		\
}

#define RK3528_CPUCLK_RATE(_prate, _aclk_m_core, _pclk_dbg)		\
{									\
	.prate = _prate,						\
	.divs = {							\
		RK3528_CLKSEL39(_aclk_m_core),				\
		RK3528_CLKSEL40(_pclk_dbg),				\
	},								\
}

static struct rockchip_cpuclk_rate_table rk3528_cpuclk_rates[] __initdata = {
	RK3528_CPUCLK_RATE(1896000000, 1, 13),
	RK3528_CPUCLK_RATE(1800000000, 1, 12),
	RK3528_CPUCLK_RATE(1704000000, 1, 11),
	RK3528_CPUCLK_RATE(1608000000, 1, 11),
	RK3528_CPUCLK_RATE(1512000000, 1, 11),
	RK3528_CPUCLK_RATE(1416000000, 1, 9),
	RK3528_CPUCLK_RATE(1296000000, 1, 8),
	RK3528_CPUCLK_RATE(1200000000, 1, 8),
	RK3528_CPUCLK_RATE(1188000000, 1, 8),

Annotation

Implementation Notes