drivers/clk/rockchip/clk-rv1103b.c
Source file repositories/reference/linux-study-clean/drivers/clk/rockchip/clk-rv1103b.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/clk/rockchip/clk-rv1103b.c- Extension
.c- Size
- 29805 bytes
- Lines
- 659
- Domain
- Driver Families
- Bucket
- drivers/clk
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/clk-provider.hlinux/of.hlinux/of_address.hdt-bindings/clock/rockchip,rv1103b-cru.hclk.h
Detected Declarations
enum rv1103b_pllsfunction rv1103b_clk_init
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2024 Rockchip Electronics Co. Ltd.
* Author: Elaine Zhang <zhangqing@rock-chips.com>
*/
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <dt-bindings/clock/rockchip,rv1103b-cru.h>
#include "clk.h"
#define RV1103B_GRF_SOC_STATUS0 0x10
#define RV1103B_FRAC_MAX_PRATE 1200000000
#define PVTPLL_SRC_SEL_PVTPLL (BIT(0) | BIT(16))
enum rv1103b_plls {
dpll,
gpll,
};
static struct rockchip_pll_rate_table rv1103b_pll_rates[] = {
/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
{ /* sentinel */ },
};
#define RV1103B_DIV_ACLK_CORE_MASK 0x1f
#define RV1103B_DIV_ACLK_CORE_SHIFT 0
#define RV1103B_DIV_PCLK_DBG_MASK 0x1f
#define RV1103B_DIV_PCLK_DBG_SHIFT 8
#define RV1103B_CLKSEL0(_aclk_core) \
{ \
.reg = RV1103B_CORECLKSEL_CON(2), \
.val = HIWORD_UPDATE(_aclk_core - 1, RV1103B_DIV_ACLK_CORE_MASK, \
RV1103B_DIV_ACLK_CORE_SHIFT), \
}
#define RV1103B_CLKSEL1(_pclk_dbg) \
{ \
.reg = RV1103B_CORECLKSEL_CON(2), \
.val = HIWORD_UPDATE(_pclk_dbg - 1, RV1103B_DIV_PCLK_DBG_MASK, \
RV1103B_DIV_PCLK_DBG_SHIFT), \
}
#define RV1103B_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
{ \
.prate = _prate, \
.divs = { \
RV1103B_CLKSEL0(_aclk_core), \
RV1103B_CLKSEL1(_pclk_dbg), \
}, \
}
static struct rockchip_cpuclk_rate_table rv1103b_cpuclk_rates[] __initdata = {
RV1103B_CPUCLK_RATE(1608000000, 4, 10),
RV1103B_CPUCLK_RATE(1512000000, 4, 10),
RV1103B_CPUCLK_RATE(1416000000, 4, 10),
RV1103B_CPUCLK_RATE(1296000000, 3, 10),
RV1103B_CPUCLK_RATE(1200000000, 3, 10),
RV1103B_CPUCLK_RATE(1188000000, 3, 8),
RV1103B_CPUCLK_RATE(1104000000, 2, 8),
RV1103B_CPUCLK_RATE(1008000000, 2, 8),
RV1103B_CPUCLK_RATE(816000000, 2, 6),
RV1103B_CPUCLK_RATE(600000000, 2, 4),
RV1103B_CPUCLK_RATE(594000000, 2, 4),
RV1103B_CPUCLK_RATE(408000000, 1, 3),
RV1103B_CPUCLK_RATE(396000000, 1, 3),
};
PNAME(mux_pll_p) = { "xin24m" };
PNAME(mux_200m_100m_p) = { "clk_gpll_div6", "clk_gpll_div12" };
PNAME(mux_gpll_24m_p) = { "gpll", "xin24m" };
PNAME(mux_480m_400m_300m_200m_p) = { "clk_gpll_div2p5", "clk_gpll_div3", "clk_gpll_div4", "clk_gpll_div6" };
PNAME(mux_480m_400m_300m_p) = { "clk_gpll_div2p5", "clk_gpll_div3", "clk_gpll_div4" };
PNAME(mux_300m_200m_p) = { "clk_gpll_div4", "clk_gpll_div6" };
PNAME(mux_600m_480m_400m_p) = { "clk_gpll_div2", "clk_gpll_div2p5", "clk_gpll_div3" };
PNAME(mux_400m_300m_p) = { "clk_gpll_div3", "clk_gpll_div4" };
PNAME(mux_100m_24m_p) = { "clk_gpll_div12", "xin24m" };
PNAME(mux_200m_24m_p) = { "clk_gpll_div6", "xin24m" };
PNAME(mux_200m_100m_50m_24m_p) = { "clk_gpll_div6", "clk_gpll_div12", "clk_gpll_div24", "xin24m" };
PNAME(mux_300m_200m_100m_p) = { "clk_gpll_div4", "clk_gpll_div6", "clk_gpll_div12" };
PNAME(sclk_uart0_src_p) = { "clk_uart0_src", "clk_uart0_frac", "xin24m" };
PNAME(sclk_uart1_src_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
PNAME(sclk_uart2_src_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
PNAME(mclk_sai_src_p) = { "clk_sai_src", "clk_sai_frac", "mclk_sai_from_io", "xin_osc0_half" };
PNAME(clk_freq_pwm0_src_p) = { "sclk_sai_from_io", "mclk_sai_from_io", "clk_testout_out" };
Annotation
- Immediate include surface: `linux/clk-provider.h`, `linux/of.h`, `linux/of_address.h`, `dt-bindings/clock/rockchip,rv1103b-cru.h`, `clk.h`.
- Detected declarations: `enum rv1103b_plls`, `function rv1103b_clk_init`.
- Atlas domain: Driver Families / drivers/clk.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.