drivers/clk/rockchip/rst-rk3562.c

Source file repositories/reference/linux-study-clean/drivers/clk/rockchip/rst-rk3562.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/rockchip/rst-rk3562.c
Extension
.c
Size
17376 bytes
Lines
430
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
 * Copyright (c) 2024 Collabora Ltd.
 * Author: Detlev Casanova <detlev.casanova@collabora.com>
 * Based on Sebastien Reichel's implementation for RK3588
 */

#include <linux/module.h>
#include <linux/of.h>
#include <dt-bindings/reset/rockchip,rk3562-cru.h>
#include "clk.h"

/* 0xff100000 + 0x0A00 */
#define RK3562_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
/* 0xff110000 + 0x0A00 */
#define RK3562_PMU0CRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit)
/* 0xff118000 + 0x0A00 */
#define RK3562_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x18000*4 + reg * 16 + bit)
/* 0xff120000 + 0x0A00 */
#define RK3562_DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit)
/* 0xff128000 + 0x0A00 */
#define RK3562_SUBDDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x28000*4 + reg * 16 + bit)
/* 0xff130000 + 0x0A00 */
#define RK3562_PERICRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit)

/* mapping table for reset ID to register offset */
static const int rk3562_register_offset[] = {
	/* SOFTRST_CON01 */
	RK3562_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 0),
	RK3562_CRU_RESET_OFFSET(SRST_A_TOP_VIO_BIU, 1, 1),
	RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_LOGIC, 1, 2),

	/* SOFTRST_CON03 */
	RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET0, 3, 0),
	RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET1, 3, 1),
	RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET2, 3, 2),
	RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET3, 3, 3),
	RK3562_CRU_RESET_OFFSET(SRST_NCORESET0, 3, 4),
	RK3562_CRU_RESET_OFFSET(SRST_NCORESET1, 3, 5),
	RK3562_CRU_RESET_OFFSET(SRST_NCORESET2, 3, 6),
	RK3562_CRU_RESET_OFFSET(SRST_NCORESET3, 3, 7),
	RK3562_CRU_RESET_OFFSET(SRST_NL2RESET, 3, 8),

	/* SOFTRST_CON04 */
	RK3562_CRU_RESET_OFFSET(SRST_DAP, 4, 9),
	RK3562_CRU_RESET_OFFSET(SRST_P_DBG_DAPLITE, 4, 10),
	RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 4, 13),

	/* SOFTRST_CON05 */
	RK3562_CRU_RESET_OFFSET(SRST_A_CORE_BIU, 5, 0),
	RK3562_CRU_RESET_OFFSET(SRST_P_CORE_BIU, 5, 1),
	RK3562_CRU_RESET_OFFSET(SRST_H_CORE_BIU, 5, 2),

	/* SOFTRST_CON06 */
	RK3562_CRU_RESET_OFFSET(SRST_A_NPU_BIU, 6, 2),
	RK3562_CRU_RESET_OFFSET(SRST_H_NPU_BIU, 6, 3),
	RK3562_CRU_RESET_OFFSET(SRST_A_RKNN, 6, 4),
	RK3562_CRU_RESET_OFFSET(SRST_H_RKNN, 6, 5),
	RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_NPU, 6, 6),

	/* SOFTRST_CON08 */
	RK3562_CRU_RESET_OFFSET(SRST_A_GPU_BIU, 8, 3),
	RK3562_CRU_RESET_OFFSET(SRST_GPU, 8, 4),
	RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_GPU, 8, 5),
	RK3562_CRU_RESET_OFFSET(SRST_GPU_BRG_BIU, 8, 8),

	/* SOFTRST_CON09 */
	RK3562_CRU_RESET_OFFSET(SRST_RKVENC_CORE, 9, 0),
	RK3562_CRU_RESET_OFFSET(SRST_A_VEPU_BIU, 9, 3),
	RK3562_CRU_RESET_OFFSET(SRST_H_VEPU_BIU, 9, 4),
	RK3562_CRU_RESET_OFFSET(SRST_A_RKVENC, 9, 5),
	RK3562_CRU_RESET_OFFSET(SRST_H_RKVENC, 9, 6),

	/* SOFTRST_CON10 */
	RK3562_CRU_RESET_OFFSET(SRST_RKVDEC_HEVC_CA, 10, 2),
	RK3562_CRU_RESET_OFFSET(SRST_A_VDPU_BIU, 10, 5),
	RK3562_CRU_RESET_OFFSET(SRST_H_VDPU_BIU, 10, 6),
	RK3562_CRU_RESET_OFFSET(SRST_A_RKVDEC, 10, 7),
	RK3562_CRU_RESET_OFFSET(SRST_H_RKVDEC, 10, 8),

	/* SOFTRST_CON11 */
	RK3562_CRU_RESET_OFFSET(SRST_A_VI_BIU, 11, 3),
	RK3562_CRU_RESET_OFFSET(SRST_H_VI_BIU, 11, 4),
	RK3562_CRU_RESET_OFFSET(SRST_P_VI_BIU, 11, 5),
	RK3562_CRU_RESET_OFFSET(SRST_ISP, 11, 8),
	RK3562_CRU_RESET_OFFSET(SRST_A_VICAP, 11, 9),
	RK3562_CRU_RESET_OFFSET(SRST_H_VICAP, 11, 10),
	RK3562_CRU_RESET_OFFSET(SRST_D_VICAP, 11, 11),
	RK3562_CRU_RESET_OFFSET(SRST_I0_VICAP, 11, 12),

Annotation

Implementation Notes