drivers/clk/rockchip/rst-rk3588.c

Source file repositories/reference/linux-study-clean/drivers/clk/rockchip/rst-rk3588.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/rockchip/rst-rk3588.c
Extension
.c
Size
37366 bytes
Lines
859
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
 * Copyright (c) 2022 Collabora Ltd.
 * Author: Sebastian Reichel <sebastian.reichel@collabora.com>
 */

#include <linux/module.h>
#include <linux/of.h>
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
#include "clk.h"

/* 0xFD7C0000 + 0x0A00 */
#define RK3588_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)

/* 0xFD7C8000 + 0x0A00 */
#define RK3588_PHPTOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit)

/* 0xFD7D0000 + 0x0A00 */
#define RK3588_SECURECRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit)

/* 0xFD7F0000 + 0x0A00 */
#define RK3588_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit)

/* mapping table for reset ID to register offset */
static const int rk3588_register_offset[] = {
	/* SOFTRST_CON01 */
	RK3588_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3),
	RK3588_CRU_RESET_OFFSET(SRST_P_TOP_BIU, 1, 4),
	RK3588_CRU_RESET_OFFSET(SRST_P_CSIPHY0, 1, 6),
	RK3588_CRU_RESET_OFFSET(SRST_CSIPHY0, 1, 7), // missing in TRM
	RK3588_CRU_RESET_OFFSET(SRST_P_CSIPHY1, 1, 8),
	RK3588_CRU_RESET_OFFSET(SRST_CSIPHY1, 1, 9), // missing in TRM
	RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M500_BIU, 1, 15),

	/* SOFTRST_CON02 */
	RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M400_BIU, 2, 0),
	RK3588_CRU_RESET_OFFSET(SRST_A_TOP_S200_BIU, 2, 1),
	RK3588_CRU_RESET_OFFSET(SRST_A_TOP_S400_BIU, 2, 2),
	RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M300_BIU, 2, 3),
	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_INIT, 2, 8),
	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_CMN, 2, 9),
	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_LANE, 2, 10),
	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_PCS, 2, 11),
	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_INIT, 2, 15),

	/* SOFTRST_CON03 */
	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_CMN, 3, 0),
	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_LANE, 3, 1),
	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_PCS, 3, 2),
	RK3588_CRU_RESET_OFFSET(SRST_DCPHY0, 3, 11), // missing in TRM
	RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY0, 3, 14),
	RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY0_GRF, 3, 15),

	/* SOFTRST_CON04 */
	RK3588_CRU_RESET_OFFSET(SRST_DCPHY1, 4, 0), // missing in TRM
	RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY1, 4, 3),
	RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY1_GRF, 4, 4),
	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CDPHY, 4, 5),
	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CSIPHY, 4, 6),
	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO3_5, 4, 7),
	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO6, 4, 8),
	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_EMMCIO, 4, 9),
	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_TOP, 4, 10),
	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_RIGHT, 4, 11),

	/* SOFTRST_CON05 */
	RK3588_CRU_RESET_OFFSET(SRST_P_CRU, 5, 0),
	RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2VO1USB, 5, 7),
	RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2CENTER, 5, 8),
	RK3588_CRU_RESET_OFFSET(SRST_H_CHANNEL_SECURE2VO1USB, 5, 14),
	RK3588_CRU_RESET_OFFSET(SRST_H_CHANNEL_SECURE2CENTER, 5, 15),

	/* SOFTRST_CON06 */
	RK3588_CRU_RESET_OFFSET(SRST_P_CHANNEL_SECURE2VO1USB, 6, 0),
	RK3588_CRU_RESET_OFFSET(SRST_P_CHANNEL_SECURE2CENTER, 6, 1),

	/* SOFTRST_CON07 */
	RK3588_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2),
	RK3588_CRU_RESET_OFFSET(SRST_P_AUDIO_BIU, 7, 3),
	RK3588_CRU_RESET_OFFSET(SRST_H_I2S0_8CH, 7, 4),
	RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_TX, 7, 7),
	RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_RX, 7, 10),
	RK3588_CRU_RESET_OFFSET(SRST_P_ACDCDIG, 7, 11),
	RK3588_CRU_RESET_OFFSET(SRST_H_I2S2_2CH, 7, 12),
	RK3588_CRU_RESET_OFFSET(SRST_H_I2S3_2CH, 7, 13),

	/* SOFTRST_CON08 */
	RK3588_CRU_RESET_OFFSET(SRST_M_I2S2_2CH, 8, 0),
	RK3588_CRU_RESET_OFFSET(SRST_M_I2S3_2CH, 8, 3),

Annotation

Implementation Notes