drivers/clk/rockchip/rst-rv1126b.c

Source file repositories/reference/linux-study-clean/drivers/clk/rockchip/rst-rv1126b.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/rockchip/rst-rv1126b.c
Extension
.c
Size
17560 bytes
Lines
444
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
 * Author: Elaine Zhang <zhangqing@rock-chips.com>
 */

#include <linux/module.h>
#include <linux/of.h>
#include <dt-bindings/reset/rockchip,rv1126b-cru.h>
#include "clk.h"

/* 0x20000000 + 0x0A00 */
#define TOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x0 * 4 + reg * 16 + bit)
/* 0x20010000 + 0x0A00 */
#define BUSCRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000 * 4 + reg * 16 + bit)
/* 0x20020000 + 0x0A00 */
#define PERICRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000 * 4 + reg * 16 + bit)
/* 0x20030000 + 0x0A00 */
#define CORECRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000 * 4 + reg * 16 + bit)
/* 0x20040000 + 0x0A00 */
#define PMUCRU_RESET_OFFSET(id, reg, bit) [id] = (0x40000 * 4 + reg * 16 + bit)
/* 0x20050000 + 0x0A00 */
#define PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x50000 * 4 + reg * 16 + bit)
/* 0x20060000 + 0x0A00 */
#define DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x60000 * 4 + reg * 16 + bit)
/* 0x20068000 + 0x0A00 */
#define SUBDDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x68000 * 4 + reg * 16 + bit)
/* 0x20070000 + 0x0A00 */
#define VICRU_RESET_OFFSET(id, reg, bit) [id] = (0x70000 * 4 + reg * 16 + bit)
/* 0x20080000 + 0x0A00 */
#define VEPUCRU_RESET_OFFSET(id, reg, bit) [id] = (0x80000 * 4 + reg * 16 + bit)
/* 0x20090000 + 0x0A00 */
#define NPUCRU_RESET_OFFSET(id, reg, bit) [id] = (0x90000 * 4 + reg * 16 + bit)
/* 0x200A0000 + 0x0A00 */
#define VDOCRU_RESET_OFFSET(id, reg, bit) [id] = (0xA0000 * 4 + reg * 16 + bit)
/* 0x200B0000 + 0x0A00 */
#define VCPCRU_RESET_OFFSET(id, reg, bit) [id] = (0xB0000 * 4 + reg * 16 + bit)

/* =================mapping table for reset ID to register offset================== */
static const int rv1126b_register_offset[] = {
	/* TOPCRU-->SOFTRST_CON00 */

	/* TOPCRU-->SOFTRST_CON15 */
	TOPCRU_RESET_OFFSET(SRST_P_CRU, 15, 1),
	TOPCRU_RESET_OFFSET(SRST_P_CRU_BIU, 15, 2),

	/* BUSCRU-->SOFTRST_CON00 */
	BUSCRU_RESET_OFFSET(SRST_A_TOP_BIU, 0, 0),
	BUSCRU_RESET_OFFSET(SRST_A_RKCE_BIU, 0, 1),
	BUSCRU_RESET_OFFSET(SRST_A_BUS_BIU, 0, 2),
	BUSCRU_RESET_OFFSET(SRST_H_BUS_BIU, 0, 3),
	BUSCRU_RESET_OFFSET(SRST_P_BUS_BIU, 0, 4),
	BUSCRU_RESET_OFFSET(SRST_P_CRU_BUS, 0, 5),
	BUSCRU_RESET_OFFSET(SRST_P_SYS_GRF, 0, 6),
	BUSCRU_RESET_OFFSET(SRST_H_BOOTROM, 0, 7),
	BUSCRU_RESET_OFFSET(SRST_A_GIC400, 0, 8),
	BUSCRU_RESET_OFFSET(SRST_A_SPINLOCK, 0, 9),
	BUSCRU_RESET_OFFSET(SRST_P_WDT_NS, 0, 10),
	BUSCRU_RESET_OFFSET(SRST_T_WDT_NS, 0, 11),

	/* BUSCRU-->SOFTRST_CON01 */
	BUSCRU_RESET_OFFSET(SRST_P_WDT_HPMCU, 1, 0),
	BUSCRU_RESET_OFFSET(SRST_T_WDT_HPMCU, 1, 1),
	BUSCRU_RESET_OFFSET(SRST_H_CACHE, 1, 2),
	BUSCRU_RESET_OFFSET(SRST_P_HPMCU_MAILBOX, 1, 3),
	BUSCRU_RESET_OFFSET(SRST_P_HPMCU_INTMUX, 1, 4),
	BUSCRU_RESET_OFFSET(SRST_HPMCU_FULL_CLUSTER, 1, 5),
	BUSCRU_RESET_OFFSET(SRST_HPMCU_PWUP, 1, 6),
	BUSCRU_RESET_OFFSET(SRST_HPMCU_ONLY_CORE, 1, 7),
	BUSCRU_RESET_OFFSET(SRST_T_HPMCU_JTAG, 1, 8),
	BUSCRU_RESET_OFFSET(SRST_P_RKDMA, 1, 11),
	BUSCRU_RESET_OFFSET(SRST_A_RKDMA, 1, 12),

	/* BUSCRU-->SOFTRST_CON02 */
	BUSCRU_RESET_OFFSET(SRST_P_DCF, 2, 0),
	BUSCRU_RESET_OFFSET(SRST_A_DCF, 2, 1),
	BUSCRU_RESET_OFFSET(SRST_H_RGA, 2, 2),
	BUSCRU_RESET_OFFSET(SRST_A_RGA, 2, 3),
	BUSCRU_RESET_OFFSET(SRST_CORE_RGA, 2, 4),
	BUSCRU_RESET_OFFSET(SRST_P_TIMER, 2, 5),
	BUSCRU_RESET_OFFSET(SRST_TIMER0, 2, 6),
	BUSCRU_RESET_OFFSET(SRST_TIMER1, 2, 7),
	BUSCRU_RESET_OFFSET(SRST_TIMER2, 2, 8),
	BUSCRU_RESET_OFFSET(SRST_TIMER3, 2, 9),
	BUSCRU_RESET_OFFSET(SRST_TIMER4, 2, 10),
	BUSCRU_RESET_OFFSET(SRST_TIMER5, 2, 11),
	BUSCRU_RESET_OFFSET(SRST_A_RKCE, 2, 12),
	BUSCRU_RESET_OFFSET(SRST_PKA_RKCE, 2, 13),
	BUSCRU_RESET_OFFSET(SRST_H_RKRNG_S, 2, 14),
	BUSCRU_RESET_OFFSET(SRST_H_RKRNG_NS, 2, 15),

Annotation

Implementation Notes