drivers/clk/samsung/clk-exynos4.c

Source file repositories/reference/linux-study-clean/drivers/clk/samsung/clk-exynos4.c

File Facts

System
Linux kernel
Corpus path
drivers/clk/samsung/clk-exynos4.c
Extension
.c
Size
57898 bytes
Lines
1422
Domain
Driver Families
Bucket
drivers/clk
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) {
			exynos4210_plls[apll].rate_table =
							exynos4210_apll_rates;
			exynos4210_plls[epll].rate_table =
							exynos4210_epll_rates;
		}

		if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24000000)
			exynos4210_plls[vpll].rate_table =
							exynos4210_vpll_rates;

		samsung_clk_register_pll(ctx, exynos4210_plls,
					ARRAY_SIZE(exynos4210_plls));
	} else {
		if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) {
			exynos4x12_plls[apll].rate_table =
							exynos4x12_apll_rates;
			exynos4x12_plls[epll].rate_table =
							exynos4x12_epll_rates;
			exynos4x12_plls[vpll].rate_table =
							exynos4x12_vpll_rates;
		}

		samsung_clk_register_pll(ctx, exynos4x12_plls,
					ARRAY_SIZE(exynos4x12_plls));
	}

	samsung_cmu_register_clocks(ctx, &cmu_info_exynos4, np);

	if (exynos4_soc == EXYNOS4210) {
		samsung_cmu_register_clocks(ctx, &cmu_info_exynos4210, np);
	} else {
		samsung_cmu_register_clocks(ctx, &cmu_info_exynos4x12, np);
		if (soc == EXYNOS4412)
			samsung_clk_register_cpu(ctx, exynos4412_cpu_clks,
					ARRAY_SIZE(exynos4412_cpu_clks));
		else
			samsung_clk_register_cpu(ctx, exynos4212_cpu_clks,
					ARRAY_SIZE(exynos4212_cpu_clks));
	}

	if (soc == EXYNOS4212 || soc == EXYNOS4412)
		exynos4x12_core_down_clock();

	samsung_clk_extended_sleep_init(reg_base, NULL,
			exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
			src_mask_suspend, ARRAY_SIZE(src_mask_suspend));
	if (exynos4_soc == EXYNOS4210)
		samsung_clk_extended_sleep_init(reg_base, NULL,
		    exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save),
		    src_mask_suspend_e4210, ARRAY_SIZE(src_mask_suspend_e4210));
	else
		samsung_clk_sleep_init(reg_base, NULL, exynos4x12_clk_save,
				       ARRAY_SIZE(exynos4x12_clk_save));

	samsung_clk_of_add_provider(np, ctx);

	pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
		"\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
		exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
		clk_hw_get_rate(hws[CLK_SCLK_APLL]),
		clk_hw_get_rate(hws[CLK_SCLK_MPLL]),
		clk_hw_get_rate(hws[CLK_SCLK_EPLL]),
		clk_hw_get_rate(hws[CLK_SCLK_VPLL]),
		clk_hw_get_rate(hws[CLK_DIV_CORE2]));
}


static void __init exynos4210_clk_init(struct device_node *np)
{
	exynos4_clk_init(np, EXYNOS4210);
}
CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init);

static void __init exynos4212_clk_init(struct device_node *np)
{
	exynos4_clk_init(np, EXYNOS4212);
}
CLK_OF_DECLARE(exynos4212_clk, "samsung,exynos4212-clock", exynos4212_clk_init);

static void __init exynos4412_clk_init(struct device_node *np)
{
	exynos4_clk_init(np, EXYNOS4412);
}
CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init);

Annotation

Implementation Notes